Hello Dimitris,
I am not sure which project you are using exactly . I can give comments based on the schematic you have attached. First of all the capacitor after your voltage divider looks like a filtering capacitor. This low pas filter will have a cut-off frequncy, fc = 1/(2*pi*(R1||R2)C) . This may be needed when you are using a switched mode regulator. Essentially you will remove any glitches from the supply from appearing using this filter. You are buffering this VDDA/2 point and is using it as the analog ground in your design. This will give you complete swing for the output(from 0 to VDDA). Your whole analog circuit is using this point as the analog ground if you observe the circuit. One of the end differential terminal is also this point.
Now bypassing is SAR ADC architecture will help you to work in a higher sample rate. Normally the maximum data rate allowable by the ADC is limited according to reference you are using. From the chip analog system point of view the with bypass capacitor the noise introduced is lesser, which will ensure error free working of all the analog components. Without the bypass capacitor the limitation will be the sampling rate. With a bypass cap, the system will be more robust with less error and interference.
Now if your application is just to know battery voltage level with PSoC 4 BLE, there is a battery level measurement example code available in PSoC Creator(File-> Code Example -> BLE_Battery_Level). Here the normal measurement method is not used.
Best Regards,
Vasanth
