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echonng
Employee
Employee
First solution authored 5 replies posted 10 sign-ins

hi,  I am using the kit - CY8CKIT-044 to build a prototype. I would like to implement auto baud rate detection for UART on the slave side. An external gateway(Master) will send a synchronization byte at the beginning of the frame (0x55u). The Slave (CY8KIT-044) shall read the first byte 0x55u through the RX pin(3.0) and calculate the baud rate time before setting the slave to the baud rate of the frame. To implement the auto baud rate detection, i am using the UART and Timer block. The timer would be triggered (reload at falling edge) and capture at rising edge to calculate the average baud rate for a number of pulses received. It would then set the UART baud rate ( by fractional divider through the Clock) to read the header & message of the frame.

I have tried out the UART & Timer in at pin 3.0 and it would work perfectly. But however i am not able to combine them together.

1)How to set the pin (3.0) to be Timer capture at the start of the transmission & later after the synchronization byte, it swaps to UART input pin (3.0) ? 

2) I am using PSOC creator. How should the schematic be amended ? 

echonng_0-1651542971910.png

 

 

1 Solution

Thanks Len.. yes, that will do..

I think i manage to figure it out the problem.. there's an input multiplexer in the psoc

echonng_0-1651819764120.png

.. When connected the Timer capture & UART block together in schematic, the input of the Timer has been selected as the initial configuration after the start up in the generated code ..

In cyfitter_cfg,

 /* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x00000090u);

echonng_1-1651820680072.png

from the HSIOM_PORT_SEL3 with config of 0x0 ,  it's indicated as connected to gpio(firmware) or dedicated hw blk (which seems to be the Timer block in this case)..

.. That's could be the reason I am not able to get the UART to work correctly..

i need to add 

CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x00000099u);

after getting time capture and setting the baud rate by fractional divider before start the uart again.. my codes seems to work after adding the config above..

 

View solution in original post

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9 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

echonng,

May I ask why you are looking to perform a auto-baud function?

Normally using the UART protocol (1 start bit; 7 to 9 data bits; 1 stop bit) can tolerate up to +/- 3% of the Master baud rate on the slave.

If you're using the UART for LIN, the specification indicates a clock accuracy of +/- 1.5%.

You labelled the one UART as UART_CAN.   CAN timing tolerance is significantly tighter.  It basically requires crystal timing since CAN is mostly peer-to-peer.  Additionally the start and stop bits do not apply to CAN protocols.

Your auto-baud sync pulses of 0x55 is very good.   Using the TImer with capture mode is a vert good plan. 

Len
"Engineering is an Art. The Art of Compromise."
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hi Len, we would like to remove the oscillator/crystal for the system cost reduction, therefore we need the slave(Psoc) on the bus should be synchronized to the master's timing. We would like to run UART over the CAN bus ( to take advantage of the differential bus for high speed) with our own proprietary protocol between the small gateway with the slave units. We do not want to run CAN protocol on this application, as you highlighted, it requires high clock accuracy & expensive software stacks.Is there any example how to do the switching of the TCPWM timer input to UART RX on pin 3.0 ? 

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

echonng,

Here's a TopDesign that successfully completes the "Build phase".

Len_CONSULTRON_0-1651673296678.png

Notes:

  • The IMO which drives Clock_1 and Clock_2 can also be trimmed improve the auto-baud.
  • The IM clock at 48MHz has a +/- 2% tolerance.
Len
"Engineering is an Art. The Art of Compromise."
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echonng
Employee
Employee
First solution authored 5 replies posted 10 sign-ins

hi Len, i believe i've tried out this before. It doesnt work. When the Pin_RX is used independently (e.g for UART only), i can receive the UART data from master. When connected both timer and UART input together, i can't receive the UART data. 

Sorry, i am new to Psoc. in the normal microcontroller i used to use, you can only assign a gpio to a specific peripheral. With this schematic, do you mean, you can assign the psoc input pins to 2 different peripherals ?  

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Is your auto-baud rate detection to get precise alignment at a fixed baud rate, e.g., 4800 baud, or is it to automatically adjust to different rates, e.g., 4800 or 9600 baud? If it's a single rate, what is your desired rate, and what level of precision do you need (+/- ?%)?
The limit on adjustment resolution is about 0.1% at 4800 baud. This is done by adjusting the divider for the clock to the UART.
---- Dennis Seguine, PSoC Applications Engineer

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hi Dennis, it's currently targetted at different baud rate (115k to 230k) depending on the network length, < +/- 3% accuracy for UART to work reliably. There's another +/-2% from RC clock of master to cater for loss of precision clock at Master. Yes, currently i am using the fractional divider for the clock to the UART.

I think I might have missed out something. Is there a need to configure the HSIOM_PORT_SELx to connect to the particular peripheral in coding after generating the code from the schematic (UART + Timer) ?  How should the snippet code looks like ?

 

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echonng,

If the only reason you're performing auto-bauding is to switch between 115K or 230K then the solution is much simpler.  The IMO which is specified to be +/- 2% accurate over temp should be sufficient.

The goal of the Timer_Counter in capture mode is to determine how many counts occur between rising edge to rising edge.   You're using a 12MHz count clock.    If the incoming 0x55 pattern from the host is about 104 counts then the baud is 115.2K.  If the count is about 52 then the baud is 230.4K.

Once you determine the incoming baud you then adjust the UART clock by adjusting the divisor by a factor of 2.

Len
"Engineering is an Art. The Art of Compromise."
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Thanks Len.. yes, that will do..

I think i manage to figure it out the problem.. there's an input multiplexer in the psoc

echonng_0-1651819764120.png

.. When connected the Timer capture & UART block together in schematic, the input of the Timer has been selected as the initial configuration after the start up in the generated code ..

In cyfitter_cfg,

 /* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x00000090u);

echonng_1-1651820680072.png

from the HSIOM_PORT_SEL3 with config of 0x0 ,  it's indicated as connected to gpio(firmware) or dedicated hw blk (which seems to be the Timer block in this case)..

.. That's could be the reason I am not able to get the UART to work correctly..

i need to add 

CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x00000099u);

after getting time capture and setting the baud rate by fractional divider before start the uart again.. my codes seems to work after adding the config above..

 

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echonng,

...

With this schematic, do you mean, you can assign the psoc input pins to 2 different peripherals ?  


Yes.  This PSoC allows to route the input to more than one peripheral input.   I tested this schematic in the "Application Build" phase and it reported NO ERRORS.

Len
"Engineering is an Art. The Art of Compromise."
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