Asking the interrupt noise in capsense raw data when it uses the CyDelayCycles function.

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GlJe_1688511
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Hello.

 

I use the CapSense and CyDelay with other interrupt(Timer and EZI2C).

 

When it uses the CyDelay, I look the Interrupt noise in capsense raw data.

 

GlJe_1688511_1-1655691946514.png

=====================================

uint32_t cydelayFreqKhz1 = 0x00005DC0;
void CyDelay1(uint32 milliseconds)
{
short *a=0,*b=0;
int32_t temp1 = 0,temp2 = 0;

while (milliseconds > CY_DELAY_MS_OVERFLOW)
{
/* This loop prevents overflow.
* At 100MHz, milliseconds * cydelayFreqKhz overflows at about 42 seconds
*/

CyDelayCycles(cydelay32kMs);
milliseconds -= CY_DELAY_MS_OVERFLOW;
}

CyDelayCycles(milliseconds * cydelayFreqKhz1);
}

==========================

If it removes the CyDelayCycles in CyDelay1, the interrupt noise in Capsense Raw data disappreared.

Why does CyDelayCycles cause Interrupt Noise?

 

Thanks and Best regards.

Glenn.

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1 Solution
PandaS
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 5 likes given

Hi Glenn,

Are there any fast-switching signals running parallel to CapSense signal trace? 

Is it possible to share the schematic files and layout for review. I find that:

I2C lines should have 330Ohm series and 4.7k Ohm parallel resistance for pull up.

VDDA AND VDDD should have separate decoupling capacitors in the layout as per datasheet and design recommendation

VCCD Should have 1uF decoupling capacitor, but you have 100nF capacitor.

 

Warm regards

Sobhit

 

 

 

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6 Replies
GlJe_1688511
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Hello.

And.

GND of my customer's board is very weak.(VSS, GND of VDD cap and VDDA cap and GND of VCCD cap)

Thanks and Best regards.

Glenn.

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PandaS
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 5 likes given

Hi Glenn,

Are you trying yo use a delay within an interrupt handler?

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GlJe_1688511
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Hello.

It doesn't use a delay within interrupt handler.

It just uses a delay within main.

I attached the sample code.

I try to reappear it on EVB.

Thanks and Best regards.

Glenn.

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GlJe_1688511
Level 4
Level 4
Distributor
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Hello.

I attached the schematic and Gerber.

GlJe_1688511_0-1655700943188.pngGlJe_1688511_1-1655700965134.png

 

Thanks and Best regards.

Glenn.

 

0 Likes
PandaS
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 5 likes given

Hi Glenn,

Are there any fast-switching signals running parallel to CapSense signal trace? 

Is it possible to share the schematic files and layout for review. I find that:

I2C lines should have 330Ohm series and 4.7k Ohm parallel resistance for pull up.

VDDA AND VDDD should have separate decoupling capacitors in the layout as per datasheet and design recommendation

VCCD Should have 1uF decoupling capacitor, but you have 100nF capacitor.

 

Warm regards

Sobhit

 

 

 

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PandaS
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 5 likes given

Hi @GlJe_1688511 ,

Thread was locked due to inactivity for long time, you can continue the discussion on the topic by opening a new thread with reference to the locked one. The continuous discussion in an inactive thread may mostly be unattended by community users.

Thanks and Regards,
Sobhit Panda
Infineon Technologies 

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