4100PS IMO clock trimming

[DaCa_4564471]

Hello,

for our application we are using CY8C4145FNQ-PS433T microcontroller from 4100PS family.

We have selected IMO as clock source and we need to communicate with an UART.

We are experiencing communication problems in our temperature range -40 °C +100°C. We lost the communication when our device is placed at Tamb > 90°c or <-25°. Even if the microcontroller work in this extended range, the 2% of tolerance over the IMO is ensured beetwen -25°C and +85°C.

So we need to ensure a lower tolerance.

As per TRM, 4100PS ha 3 registers for clock trimming purpose.

CLK_IMO_TRIM1 and CLK_IMO_TRIM1 provides the frequency trimming and CLK_IMO_TRIM3 the temperature compensation.

My questions are:

1 - Are CLK_IMO_TRIM1 and CLK_IMO_TRIM2 provided with manufacturing values by Cypress? Or do we have to set up a trimming phase in our production line, changing these values comparing them with an external clock reference?

2 - Can we change CLK_IMO_TRIM1 and CLK_IMO_TRIM2 run time in our fw ( even if I don't konw how, without having a clock reference)?

3 - Is there an algorithm to follow to implement the temperature compesantion? We can read both Die Temperatura or pcb temperature wiht an NTC, but I Think Die Temperature is better beacuse placed near the IMO.

Thank you

Daniele Cavazza

[Vasanth · Accepted solution]

Hi,

1)

 IMO TRIM1 : Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting
(IMO_TRIM2) and stored in SFLASH. This field is mapped to the most significant bits of the IMO
trim imo_clk_trim[10:3]. The step size of 1 LSB on this field is approximately 120 kHz.
Default Value: 128

IMO TRIM2: Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is mapped to the least significant bits of the IMO trim imo_clk_trim[2:0].
The step size of 1 LSB on this field is approximately 15 kHz.
Default Value: 0

IMO TRIM3: These bits are determined at manufacturing time to compensate for temperature and process  variation. 

2) You can change both those registers. You can use a higher accuracy clock to trim.

This old example can be used as reference but cannot used directly. https://www.cypress.com/documentation/code-examples/ce97601-improving-accuracy-psoc-4-internal-main-...

Best Regards,
Vasanth

[DaCa_4564471]

Thanks @Vasanth ,

this is more or less what was on my mind.

And what about temperatura compensation?

How the value of IMO TRIM3 change the IMO Clock?

Can I change this value runtime if I see a Clock frequency variation over temperature?

Thank you

[Vasanth]

Hi,

Regarding the temperature TRIM, Trim settings are generated during manufacturing for every frequency that can be selected by CLK_IMO_SELECT. These trim settings are stored in SFLASH. It is recommended to use the provided values but you do have an option to update the TRIM values following an algorithm.

Please check figure 9-2 in https://www.cypress.com/file/280681/download

Best Regards,
Vasanth

[DaCa_4564471]

Hi, 

the algorithm you mentioned is the same shown in the TRM Manual. I supposed this was only to trim the frequency with TCTRIM1 and TCTRIM2.

I was searching for a formula similar to the one shown in the following AN

PowerPSoC® – Improving IMO Frequency Accuracy over a Wide Temperature Range (cypress.com)

Do you know if PSOC4100PS implement a similar formula or a different one?

Thank you

Best Regards,

Daniele Cavazza