What can we do to test linearity (INL) of 12bit SAR ADC with sinusoidal signal source which has only 10bit DAC ?
Simply put how can i increase linearity performance of 10bit DAC source?
Appriciate your comments
Is there a reason you are restricted to a 10 bit DAC? Why not using one with a higher resolution (even using 12-bit one will give you the problem that the DAC itself might not be linear).
And what is the reason for you to test the linearity of the ADC at all?
Thank you @hli
Its more of query whether it is possible to improve linearity of DAC by any simple means.
If we wanted to use 10bit source and improve its SNR then we could just use a bandpass filter followed by buffer ryt ?
In a similar way is there anything we could do to improve linearity of source, if yes please explain briefly.
The following might assist -
Improve non linearity http://www.cypress.com/?docID=32344
Yopur original question was about resolution, not about linearity of the DAC. So now I'm confused...
If you want to improve the resolution, look at the documents Dana I gave you. They show multiple ways to increase the resolution of the PSoC IDACs up to 12 bit. If you need better resolution, you can a PWM as DAC as PSoC73 suggested.
If you want to improve the DACs linearity, ask Dana, she knows her stuff 🙂 (Much better than I do, I should add...)
It might be useful if you could shed some light on -
1) Target specs needed, DC, AC, temp, noise......
2) Application, what is the DAC output being used for
A filter and buffer can improve noise performance, or destroy it, it all
depends on specs you are trying to achieve and how you implement
the additional signal path components. As you approach higher perfformance
very subtle effects cause increasing problems, like the crossover distortion
in the input of R-R OpAmps the industry does not like to talk about.....
@hli my question was how can i improve the linearity of 10 bit DAC such that it is equivalent to a 12bit DAC source.
@dana application my source is limited and i would like add some external circuitry to improve its linearity so that i can test ADC with that. So the question is what external circuitary should i add to serve this purpose ?
Your first question, dithering, per link posted in prior part of thread.
One approach to SAR testing, use 16 bit PWM with integrator ( R-C network ), DelSig to read PWM
output of R-C, and feed R-C to SAR. Since DelSig good to 20 bits, that in turn insures you know what
the V source (PWM) is doing, and measure against SAR output. I would use averaging on readings to eliminate
Scratch the SAR testing comment in prior post, forgot there is no DelSig
in PSOC 4.
If you used 16 bit PWM approach, and supplied a precision reference for Vdd on the
part, then PWM would in effect become a precision DAC. Note this is only if you need
absolute accuracy. If all you need is relative no reference is necessary. The PWM is
inherently montonic, only its output integrator, if you used an OpAmp integrator vs the
simple R-C network, would affect montonicity.
Did you look at the first two links Dana gave you? The contain an AppNote about increasing the resolution of the PSoC DACs, and even a complete dithered VDAC (which I didn't knew existed as finished component - thanks for pointing me to it, Dana!)
"yields a DC outoput directly proportional to DC."
That might be confusing in prior post, should be
"yields a DC output directly proportional to Duty Cycle."