When you want fair comparisons made while looking at the cycle to cycle jitter numbers, there are few points to remember as follows:
As specified in JESD65B spec, cycle to cycle jitter requires at least 1000 samples to be taken. So while comparing one should see if the measurements are made with the same number of samples. More samples will have more data resulting in bigger jitter value and less samples have less data resulting in lesser jitter value.
Also, JESD65B spec says that the cycle to cycle jitter should be mentioned as a peak value. So if any datasheet mentions that to be peak to peak measured, the actual cycle to cycle jitter peak value becomes half.
For fullproof comparison, request samples and measure with the same equipment and conditions.Show Less
Cycle to Cycle type of jitter has a random (i.e. Gaussian) distribution, the tails of this distribution are unbounded, and therefore the "worst-case" jitter you'll see from any device will always increase the longer you measure it. This is just a simple fact of nature, and is common from all manufactured parts, at Cypress as well as other companies. This may give you an unsettled feeling at first, but keep in mind that although the worst-case jitter you measure with time will always increase, the probability of getting that jitter is always decreasing, so in the end, you should stop measuring jitter because the chance of seeing a larger jitter number is so small you'll have to wait days, weeks, years, to see an increase in the last measured "worst-case" jitter number.Show Less
The typical peak-peak period jitter value is completely determined by the configuration of the device. In general, jitter can be reduced by using the least number of outputs and PLL's, or using smaller Q values. We can optimize the parameters P and Q. You can calculate the P and Q values using the Cyberclocks software, available on our website. The jitter varies with the different configurations. There are certain factors that help in minimizing jitter for a particular configuration.
Your jitter will be reduced when you minimize the number of PLL's running on the die. The worst case jitter depends on how many outputs and PLL's are running as well as what combinations of frequencies are running on the chip.
Keeping VCO frequencies high as possible will always give you better jitter performance. The way to minimize jitter is to run the minimum number of outputs and PLL's. Also having clean multiples of the input frequency will help reduce jitter in some cases as well.
Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.
So with a lower frequency, either your VCO is running slower which increases jitter, or you are using a larger divider value which can also increase the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.
So again, in cases where reducing jitter is of paramount importance, it is recommended running fewer PLLs in case of multi-PLL devices.
If you are finding any difficulties getting crystal with the specifications in the CY24293, look at the Abracon ABLS series that meets the specs. Attached is the datasheet.Show Less
For the CY22050 and CY22150, the AVDD powers the PLL, VDD powers the crystal oscillator and CLK5 and CLK6, and VDDL powers LCLK1-LCLK4. You should bring up both VDD and AVDD with a smooth monotonic ramp, but VDDL can be powered up or down at any time. Powering it down while still powering AVDD and VDD is not a problem.
During power up, important events takes place where the start up registers are loaded to put the part in a start-up condition. If the power ramp is not monotonic, the start up conditions will be lost and the device may come in an unknown state and not behave as expected. So it is recommended that the power ramp specification be applied as specified in the datasheets.Show Less
I need to set the register of CYII5SM1300AB through Serial 3-Wire Interface;
I have find a few infomation of the serial 3-wire interface, and there is not the interface timing;
Where can i get it.
And i can't find how to load the value to the interal register.
Another question, the description of Pin 4( S_DATA), it's an digital input/output, so can i read the register value through the serial 3-wire interface, and how to realize it.
Thanks and please help me!
Always look and go for Spread Aware Clock Buffers for signal distribution when you want Spread Spectrum signal to pass as they have larger close loop bandwidth. Normal Clock Buffers will filter the spread spectrum signal. Cypress has such buffers with an “S” in the part number. Examples are CY23S02, CY23S05, CY23S08 and CY23S09 with 2, 5, 8 and 9 outputs respectively.
Check Clocks and Buffers Product Selector Guide for detailed part numbers at (Devices are listed on page 11):Show Less
Check out the different devices in the new High Performance Buffer (HPB) family with ultra low-jitter non-PLL clock fanout buffers that delivers up to 10 high-frequency (up to 1.5GHz) differential outputs (LVPECL, LVDS, or CML).
Following is the link for the Parametric Search page that Provides a list of devices in Production:Show Less
Find the clock basics covered in this book in various chapters. I find this to be equivalent to what one can call as Cypress’s Bible to Clocks and Buffers! Post your questions here! The authors themselves might answer.
Following is the link to the book on Cypress Website:Show Less