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I would like to use NovalithIC™ BTN7970 High Current PN Half Bridge, at the switching frequency ~1 kHz. The trouble is that I need to modulate pin No. 3 (Inhibit) as well to disable reverse current through the lower switches (therefore it would be switched at ~2 kHz). Is this possible, can BTN7970 respond properly to such relatively fast switching of this pin, since it goes to "sleep mode"?
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Hello,
We are working on a new desing using CY22393 programmable PLL to generates a synchronous clock from another.
We have calculated P and Q dividers and post div values and would like to check that they are compliant with your internal component constraints using your CYClocksRT software but there is no way to enter manualy que P Q and post div values in this software.
The sofware only works from enterred frequencies values, but it does not calculates the same P and Q values has we have determined and the obtained output frequency is less accurate than the one using our calculted values.
For example our input frequency is 27 * (1000 / 1001) MHz so approximatively 26,973027 MHz
We want to output a precise 9.6 MHz frequency and we have determined that it can be precisely generated using the following values :
P= 2002
Q= 225
post div = 25
Do these values match our component internal constraints ? There is no precision in the datasheet about these constraints, just a instructions to use CyClocksRT software.
But the sofware doesn't the calculated the values we want to use the obtained frequency is not as exact as what we can get.
In our example the software computes the following values :
P= 867
Q= 84
post div = 29
Frequency output = : 9,60000590 MHz frequency
Thank your for your support,
Best regards,
Corentin
Show LessI'm not sure if this is the right forum to post this question -- I've not seen much on the CY22801. Despite reading the data sheet several times, I'm still not sure of a few things regarding programming and operation.
I see that the programmer kit CY36800 can be used for this part. One question on this programmer: does it only program the part before being soldered in circuit? If so, I assume it has a socket for the SOIC8 part -- the photos are pretty poor quality to be able to confirm this. Can this programmer do ISP/ICP in system programming?
OK, once the part is programmed, and I am considering a fairly simple example: 10 MHz external input, 150 MHz output on CLKA. After the part starts up, there should be the proper frequency on the output Clock A. At this point, can the frequency be changed with the use of I2C serial programming on pins 3 and 5? It is my understanding that the original programmed output (150 MHz in this example) will come up each time the part is powered up and that the I2C programming will not, and needs to be done each time.
Now, if the previous paragraph is true, how does one use the JEDEC file to change the frequency via I2C?
Is my understanding of the programmer and the CY22801 part correct? If not, where have I gone astray?
Thanks, Don.
Show LessIn a ‘customized’ PLL, the Q, P, and the Post-Divider are mask-programmed in a ROM. They have Fixed values and fixed frequencies.
The Drawbacks of non-programmable PLL based devices are:
1. Design (i.e. frequency) changes can be costly and time-consuming.
2. Long lead times for new custom solutions.
3. Searching for a new fixed-function part.
With Cypress programmable clock chips, the Q, P, and the Post-Divider are programmable in EPROM or EEPROM. Design changes are fast, easy and flexible. Programming a new set of P, Q, and Post-Divider values allows for design changes throughout project development.
To summarize, Cypress has Programmable synthesizers, EMI Reducing clock generators, VCXO based devices and programmable crystal oscillators that have following key advantages:
• Programmable technology allows fast prototype builds
• Generates a wide range of frequencies using low cost crystals (Xtals)
• Multi-PLL devices integrates multiple Xtals/ XOs reducing cost
• VCXO option for tuning frequency
• Spread Spectrum option for reducing EMI at its source
• Low Jitter for maximizing system reliability
• Specialty Clocks for applications in Handsets, PCI, XDR Rambus
• Low Power for portable applications
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Cypress is continuously improving the collateral to meet customer satisfaction. As a part of it application note: AN52133 – Frequency Margining using FleXO(TM) and Its Applications is updated as per customer’s feedback. Please review and provide your valuable feedback on the survey that will follow after the review.
The latest copy of Application Note is available on following link:
http://www.cypress.com/?rID=35389
The High Performance Buffer products are ideally suited for systems that have a large number of high-speed interface ports (e.g., Gigabit Ethernet) or a large number of components, each requiring a copy of identical clock frequencies with minimal additive phase jitter to ensure good system timing margin.
HPB is used in a variety of applications or systems with high-speed serial (SERDES) interfaces that require differential clocks such as:
Platforms: Switches and routers, Wireless base stations, Optical networking (PON, MSTP, etc.), Blade servers, Test equipment.
High-speed interfaces: Gigabit/10-Gigabit Ethernet (GbE, 10GbE), PCI-Express, FibreChannel, SONET/SDH, CPRI.
More Areas: FPGAs, Network Processors, PLDs, Framers, PHYs.
Show LessIf you're using a crystal reference, then the load capacitance can be set to a value within 6 pF to 30pF range with increments of 0.375 pF. This is done by programming a 6 bit internal register. If a driven reference is used, then this register is set to provide 6pf total (12pf on each leg of the crystal) and since XTALOUT must be left floating, the input cap load in this case, is 12 pF.
The default value in CyClocksRT software where you set this is 18.19pF for a crystal selected as a reference. So you can select a crystal of your desired frequency value (within the range specified) with 18pF load and enter the frequency value (MHz) in the REF entry box provided. You need not provide external caps to match the crystal load.
Show LessGenerally the VDD pin draws more current. The AVDD pin powers the core and the PLL's, while the VDD pin powers the clock outputs. It is frequency and configuration dependant for the CY22392F. When you use CyClocksRT of CyberClocks Suite, there is a Current Consumption display in the Advanced GUI section which shows the total amount of current the device will typically need. By clicking on each of output suspend box you can see how much current that particular output consumes by subtracting the total current consumption before and after selecting the suspend option.
If all PLL's are running around 400MHz the AVDD will draw around 20mA, if all PLL's are running around 200MHz the AVDD will draw around 12mA and if all PLL's are running around 100MHz the AVDD will draw around 8mA.
You can subtract the AVDD value from the total current consumption to get the VDD current.
It is recommended connecting the Shutdown/OE pin to VDD or GND to be on the safe side. However, a 5ms pulse for Shutdown pin should not be a problem. The shutdown signal should propagate in nano seconds, the PLL and outputs should be turned off in micro seconds and the oscillator should be off in milli seconds for the CY22392.
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