Other Technologies Forum Discussions

Are HOTLink II devices upward compatible with HOTLink devices?

Is it possible to use a HOTLink II device to the HOTLink protocol?

For example, can CYP15G0101DXB be used to replace CY7B923 / 933?

It is using CY7B922 / 933 in current product. I want to realize HOT Link with the next model. I would like to know if HOT Link II devices can be used with the following models.

As far as I read AN1160, I think it can be used.

Thanks,

Tetsuo

Hello,

Can somebody help me with the FIT or MTBF value of the SIT8008BI-11-18E-100.000000 oscillator?

Thanks in advance.

Hi,

I found the firmware (.img) of a cmos sensor from onsemiconductor on their website. Is it possible to read the source code of the .img file?

Many thanks,

Frank

Hello,

I have questions below parameters in CY2308 datasheet.

1) t6 Delay, REF rising edge to FBK rising edge :  max +/-250ps

Please tell me the meaning of this regulation.

I understand that this rule is not the input condition of the clock buffer, but the maximum value of the phase shift between the REF input and the FBK input when the PLL of the clock buffer is synchronized. Is my understanding correct?

(The clock buffer keeps the deviation between the REF input and the FBK input within this value.)

2) CL, Load capacitance, below 100 MHz : max 30pF

Regarding the capacitance to be added to the CLK A1 output returned to the FBK pin, what will happen if a capacitance exceeding the specified 30 [pF] is added?

In my opinion, the slope of the voltage rise / fall of the FBK input becomes smaller, and the graph of load capacitance and delay difference specified in the application note is no longer in a linear relationship.

(Therefore, the amount of delay with respect to the load capacity varies greatly from component to component).

However, although the variation will be large, I think that the PLL will not be unlocked.

Or, if other behavior (such as PLL lock cannot be guaranteed) is expected, please let me know the behavior.

MPN : CY2308ZXI-1HT

I referred to the information in the link below.

CY2308 Datasheet

https://www.cypress.com/file/38856/download

AN1234 - Understanding Cypress’s Zero Delay Buffers

https://www.cypress.com/documentation/application-notes/an1234-understanding-cypress-s-zero-delay-buffers

Best Regards,

Naoaki Morimoto

On the last delivery of the subject components the "Dot" representing Pin 1 appears on the lower left side

instead of the upper left side while the printing text is left to right (see picture).

Who may advise on Where is the real Pin 1 ???