Are HOTLink II devices upward compatible with HOTLink devices?
Is it possible to use a HOTLink II device to the HOTLink protocol?
For example, can CYP15G0101DXB be used to replace CY7B923 / 933?
It is using CY7B922 / 933 in current product. I want to realize HOT Link with the next model. I would like to know if HOT Link II devices can be used with the following models.
As far as I read AN1160, I think it can be used.
Can somebody help me with the FIT or MTBF value of the SIT8008BI-11-18E-100.000000 oscillator?
Thanks in advance.Show Less
I found the firmware (.img) of a cmos sensor from onsemiconductor on their website. Is it possible to read the source code of the .img file?
The MCU must be an MCU with a built-in 2-channel Ethernet control circuits.
And those Ethernet control circuits must meet the following conditions.
1) Receive all frames
The 2ch built-in Ethernet circuits should not receive only the unique MAC address assigned to each channel.
Instead, those circuits must be able to receive Ethernet frames addressed to all MAC addresses.
And those received frames need to be able to be processed by the software.
2) Spoofing transmission
The 2ch built-in Ethernet circuits should not send Ethernet frames with the unique MAC address assigned to each as the source address.
Instead, those circuits need to be able to set any address as the source MAC address of the Ethernet frame they send.
That is, one network device must impersonate multiple independent network devices with arbitrary MAC addresses.
3) Interrupt during reception
When receiving an Ethernet frame, it is necessary to generate a receive interrupt before receiving the end of the frame.
For example, a receive interrupt must be generated when the Ehernet header is received, and the software must be able to perform data processing in response to the interrupt.
Furthermore, as a more desirable specification, it would be nice if an interrupt could be generated when an arbitrary size was received from the beginning of the frame.
Could you introduce an MCU with a built-in 2ch Etehrnet control circuits that meets the above three conditions and an evaluation board equipped with it?
Currently, we are considering the adoption of the evaluation board "KIT_A2G_TC377_SEC_GTW" equipped with "AURIX TC377TX".
I would like to understand in deeper for the following topics,
1.Detailed difference between DSPR, PSPR, DCACHE, PCACHE, LMU & PMU (PFLASH, DFLASH) memory units. - As I know PMU is Flash and remaining all are RAM
2. How the data processing of LMU is slow as compared to DSPR/PSPR
3. How differs the Latency to access for the following,
i. inter core DSPR/PSPR,
iii. Intra core DSPR/PSPR Show Less
I'm working on IRPS5401. I programmed the device with configuration file that i got from zcu104. At first when I try modify some registers and write it into IRPS5401 registers it works okay after i power cycle the device but after some time I2C does not get any address from device and device remain undetected on PowIRCenter GUI. The device is not showing any voltage on switchers.
KINDLY HELP ME SO THAT I CAN WORK ON MY SILENT IRPS5401 DEVICES. Show Less
I Have this regulator and is not detectable on I2C and therefore I can't check what is happening with regulator so can I erase all data stored previously in NVM and program this device from scratch? Show Less
I have questions below parameters in CY2308 datasheet.
1) t6 Delay, REF rising edge to FBK rising edge : max +/-250ps
Please tell me the meaning of this regulation.
I understand that this rule is not the input condition of the clock buffer, but the maximum value of the phase shift between the REF input and the FBK input when the PLL of the clock buffer is synchronized. Is my understanding correct?
(The clock buffer keeps the deviation between the REF input and the FBK input within this value.)
2) CL, Load capacitance, below 100 MHz : max 30pF
Regarding the capacitance to be added to the CLK A1 output returned to the FBK pin, what will happen if a capacitance exceeding the specified 30 [pF] is added?
In my opinion, the slope of the voltage rise / fall of the FBK input becomes smaller, and the graph of load capacitance and delay difference specified in the application note is no longer in a linear relationship.
(Therefore, the amount of delay with respect to the load capacity varies greatly from component to component).
However, although the variation will be large, I think that the PLL will not be unlocked.
Or, if other behavior (such as PLL lock cannot be guaranteed) is expected, please let me know the behavior.
MPN : CY2308ZXI-1HT
I referred to the information in the link below.
AN1234 - Understanding Cypress’s Zero Delay Buffers
Naoaki MorimotoShow Less
On the last delivery of the subject components the "Dot" representing Pin 1 appears on the lower left side
instead of the upper left side while the printing text is left to right (see picture).
Who may advise on Where is the real Pin 1 ???Show Less
We have connceted the 2hp induction board with Eval M3 Im564 and Eval 102t but is showing the motor fault As we have not written any code we have enetred the script file which was generated in the mce wizard,could u please help me with that regarding problem. Show Less