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I am looking at the Datasheet for the Cypress CY29948 low-voltage 200 MHz clock distribution buffer it states that unused pins must be tied to the proper voltage level. But since some of the input pins have internal pull-ups, that defaults to the voltage required for the unused pin, is using the internal pull-up acceptable? 

Hello, 

I am currently in the process of finding a replacement for the CY37128P100-AXC which was discontinued a while ago. I was wondering if there were any products which were similar in form, fit and function to the 128P100-AXC CPLD which cypress manufactures. If not do, is there any other CPLD which could replace the CY37128P100-AXC.

Hello,

I have a question about the Cypress clock buffer (CY2308ZXI-1HT).

The Switching Characteristics parameter t5 specifies the output skew between each port of the output terminals CLKA1 to 4 and CLKB1 to 4.

t5 is,
- using internal PLL (S2 = 1, S1 = 1)
- does not use the internal PLL (S2 = 1, S1 = 0) (= Mode that outputs the REF clock signal)
In either case, is the output skew between each port specified by t5?

MPN: CY2308ZXI-1HT

Data sheet "Document Number: 38-07146 Rev. * T"
https://www.cypress.com/file/38856/download

Best Regards,

Naoaki Morimoto