spi interface with SLM9670

[alex7]

Hi,

There is a tpm device SLM9670 connected to NXP CPU with SPI bus on my board. The running linux version is 4.14. spi mode is 0.

From tpm_tis_core driver tpm startup, SPI master send 0x80-0xd4-0x0-0x0 to SLM9670, SLM9670 responses 0x0-0x0-0x0-0x1 at first transaction, then TPM ACCESS VALID(0x80) at second transaction.

But on my board, SLM9670 response 0x0-0x0-0x0-0x1. then 0x0. Could you please tell me why SLM9670 cannot response TPM ACCESS VALID?  thanks.

Please see the SPI bus waves captured by probe.

red: SCK

yellow: MOSI

blue: MISO

[Sneha_P]

Hi @alex7 ,

Could you please specify what board you are referring to. Also could you share the hardware connection from your board to SLM9670. 
In the scenario when it detects the TPM, are you using a different host?

[alex7]

Hi Snehapra,

SLM9670 is connected to NXP t1042 CPU by SPI interface on our board. And CPU CS2 is assigned to SLM9670. CS0 and CS1 are assigned to EEPROM which works well. 

SLM9670 schematic(tpm_slm9670.pdf) was attached.

TPM cannot be detected from tpm-tis-spi driver. it's the  same host(T1042).

Does both MOSI/MISO need to be pull up to 3.3V? MISO does not be pulled up on our board.  Why high level MISO cannot reach to 3.3V from my captured wave?

[Sneha_P]

Hi @alex7 ,

CS2 must be low (active) in case the TPM is interacting with the host system. It must stay high in case the TPM is not addressed. Could you confirm the same?

[alex7]

Hi Snehapra,

Yes. CS2 is active during SPI bus transaction. otherwise SLM9670 does not response the 0x0-0x0-0x0-0x1 from spi--00003.jpg.

BR.

[Sneha_P]

Hi @alex7 ,

Could you share the VDD and RST probe traces when power on? Also, what is SPI frequency in your design?

[alex7]

Hi Snehapra,

Attachment is VDD and RST wave when power on. And spi frequency is 2.4Mhz.

[Sneha_P]

Hi @alex7 ,

Could you clarify if the power-up VDD starts from ~1.4V?
Also, have you mounted the TPM on motherboard or is it fly wiring? Can you share a screenshot to identify this?
And in regard to your schematic, we recommend removing R471 and R534

[alex7]

Hi Snehapra,

HW guys is investigating the VDD ~1.4V issue. Does the VDD power up issue impact TPM device?

TPM device is connected to NXP CPU on our board. No fly wiring.

It's the same result after removing R471 and R534.

[Sneha_P · Accepted solution]

Hi @alex7 ,

The timing of Cold(Power-On) Reset tPOR min is 80us as stated in section 5.5 of Infineon Datasheet: https://www.infineon.com/cms/en/product/security-smart-card-solutions/optiga-embedded-security-solut... 

And you can find the Input voltage low VIL max 0.3Vdd of RST# in table10. Your values are out of this range.

[alex7]

Hi Snehapra,

We capture the tpm power and reset signal again. Could you please check if it can meet the requirement of tpm? thanks.

[Sneha_P]

Hi @alex7 ,

The resulting waveform shows several steps of Vdd power, which does not meet the SCLK slew rate requirement in the Infineon datasheet.
Please follow the data and characteristics stated in the Infineon datasheet when enabling TPM on your device. 

https://www.infineon.com/dgdl/Infineon-SLM%209670-DataSheet-v01_00-EN.pdf?fileId=5546d46269e1c019016... 

It would be great if can also set up an RPi platform according to Infineon AppNote as a good reference to enable the TPM driver.

[alex7]

Hi Snehapra,

I attached 3V3 and SPI_CLK during powerup and SPI_CLK clock waves. Looks no SCLK slew.

CPU_SPI_CLK was high during powerup, then it went low after CPU and FPGA initialization, it needed sometime to finish that. There was no SPI_CLK during powerup, it would generate the clock when we sent commands from CPU side.

CLK_SPI: its frequency was 1.953421MHz, according to the test result, the slew rate was >=1V/ns and the typical VDD was 3.3V, so it could meet chip’s requirement if the frequency was less than 43MHz.

[Sneha_P]

Hi @alex7 ,

Could you help provide and clarify following items:
1. Please send us the SPI waveforms which do not overlap, and which also includes CS with corresponding color and names
2. the SPI and CS0 and CS1 waveform status of EEPROM during TPM is mainly communicated by host when CS2 is active?
3. for SCLK slew rate, can you send us the higher resolution waveforms showing rising/falling time between 0.2Vdd and 0.6Vdd?
4. As SPI bus is shared with other two devices (EEPROM), can you send us the data sheet from the NXP SPI master available?

BR,

Sneha

[Sneha_P]

Hi @alex7 ,

Please provide the requested details for further investigation.

Thanks,

Sneha

[Sneha_P]

Hi @alex7 ,

Please confirm if this thread can be closed as another communication channel is established for the same issue.

Thanks,

Sneha

[alex7]

Hi Snehapra,

Yes. Please close it. thanks.