Thank you for contacting Infineon Technology. Please see below
Firstly I assume you have already enabled QPI mode (4-4-4), which Configuration Register2 QPI-IT bit is configured as 1. To program data into flash in 4S-4S-4S mode, send Write Enable command (0x06), then send command 0x02 (or 0x12) following start address and input data. All input data (including command code, address and data) should be sent on four IO pins. If using 0x02 program command, if Configuration Register2 bit7 (ADRBYT) is 0, 3-byte address is required; if ADTBYT=1, 4-byte address is required. If using 0x12 program command, 4-byte address is always required. The address is the start address where the data started to be programmed. And the next input data is automatically programmed into the next sequential address. No need to input the next addresses. One transaction can program any number bytes of data between one byte up to 256 bytes if Configuration Register3 bit4 (PGMBUF) is 0 (or up to 512 bytes data if PGMBUF=1). The addresses of the multiple memory locations to be programmed in one transaction must be consecutive. For example, programming data into 0x0000 0000 to 0x0000 00FF can be done with one transaction (start address following program command is 0x0000 0000). But programming data into 0x0000 0000 to 0x0000 000F and 0x0000 0020 to 0x0000 002F needs two transactions – one transaction start address is 0x0000 0000, the other transaction start address is 0x0000 0020.
Similar as program operation, to read in 4S-4S-4S mode, Configuration Register2 QPI-IT bit needs to be 1 and all input data (command code and address) need to be sent on four IO pins. 4-4-4 read commands are 0xEB, 0x0C and 0xEC (please refer to datasheet for the differences of these commands). Sending read command code following start address, then the consecutive data will be output sequentially starting from the start address, until CS# signal is pulled high. The read operation can read the entire memory space with one transaction if keeping CS# low. Same as programming operation, if the read addresses are not consecutive, multiple transactions are needed.
Thank you for contacting Infineon Technology. Please see below
Firstly I assume you have already enabled QPI mode (4-4-4), which Configuration Register2 QPI-IT bit is configured as 1. To program data into flash in 4S-4S-4S mode, send Write Enable command (0x06), then send command 0x02 (or 0x12) following start address and input data. All input data (including command code, address and data) should be sent on four IO pins. If using 0x02 program command, if Configuration Register2 bit7 (ADRBYT) is 0, 3-byte address is required; if ADTBYT=1, 4-byte address is required. If using 0x12 program command, 4-byte address is always required. The address is the start address where the data started to be programmed. And the next input data is automatically programmed into the next sequential address. No need to input the next addresses. One transaction can program any number bytes of data between one byte up to 256 bytes if Configuration Register3 bit4 (PGMBUF) is 0 (or up to 512 bytes data if PGMBUF=1). The addresses of the multiple memory locations to be programmed in one transaction must be consecutive. For example, programming data into 0x0000 0000 to 0x0000 00FF can be done with one transaction (start address following program command is 0x0000 0000). But programming data into 0x0000 0000 to 0x0000 000F and 0x0000 0020 to 0x0000 002F needs two transactions – one transaction start address is 0x0000 0000, the other transaction start address is 0x0000 0020.
Similar as program operation, to read in 4S-4S-4S mode, Configuration Register2 QPI-IT bit needs to be 1 and all input data (command code and address) need to be sent on four IO pins. 4-4-4 read commands are 0xEB, 0x0C and 0xEC (please refer to datasheet for the differences of these commands). Sending read command code following start address, then the consecutive data will be output sequentially starting from the start address, until CS# signal is pulled high. The read operation can read the entire memory space with one transaction if keeping CS# low. Same as programming operation, if the read addresses are not consecutive, multiple transactions are needed.
