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I had an issue with the 4READ command.
Data is output one clock later than expected.
It seems that the change_addr signal is to blame: it fires depending on the ADS bit at 24 or32 bit boundary.
For commands configurable between 3/4 byte addresses this is correct, but i.m.o. 4READ always is 4 byte address,
so change_addr should always fire at32 bit boundary.
Please check whether assumption above is correct.
Regards, Wim
My code mod to remove issue:
IF (current_state /= STANDBY) AND
(Instruct /= WRR) AND (Instruct /= WRAR) THEN
IF ((Instruct = READ) AND to_nat(WRR_reg_in) = 0) OR Instruct /= READ THEN
-- IF ADS = '1' AND address_cnt = 32 THEN
IF address_cnt = 32 THEN
change_addr <= '1', '0' AFTER 1 ns;
ELSIF ADS = '0' AND address_cnt = 24 THEN
change_addr <= '1', '0' AFTER 1 ns;
END IF;
END IF;
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Hi Wim,
- Could you please tell me the version of the model you are using?
- Could you also tell me whether you are using SDF file or not?
Thank you and Regards.
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Hi,
I do not use the SDF file, only vhdl sources, compiled in Questasim.
Model version:
# Release Date (DD/MM/YYYY) => 08/06/2018
# Release Version => 1.3
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Hi,
I would request you to repeat the simulation using the SDF file. If the issue persists, please do let me know.
Regards.