The S29AL008J70BFI010 datasheet lists the sector trace time as "10s",
The S29AL008J70BFI010 datasheet lists a maximum sector trace time of 10s.
I understand from the above description that if it takes more than 10 seconds to execute a sector trace, it is considered to be abnormal, Is this correct?

Hello,

I am using S25FS512SAGNFI011 Nor Flash for the FPGA Arria 10 configuration. I generated .jic file from .sof file as described in the document AN229767 of Infineon. I get the successful result on the tool when I load the file to the flash, but the FPGA does not boot up after power cycle. 

My settings for the generating the file are below:

I'll be glad if you can help me.

Best regards!

While attempting to flash data onto the memory, we have encountered persistent problems with memory corruption and functionality. Specifically, we have observed that errors are consistently popping up within the address range of 0x00000000 to 0x00002800. 

 Also, while erasing memory errors are popping up in given images

We've tried troubleshooting but need urgent assistance to resolve this issue.

Thanks & Regards

PSCK/tCH/tCL are available as AC specifications for SCK duty ratio, and for tCH/tCL, Notes 30,
Notes 30. ±10% duty cycle is supported for frequencies ≦ 50MHz.
(Confirm AC specs regarding SCK duty ratio: tCH/tCL)
When using SCK frequency: 333 kHz (PSCK: 3000 ns [cycle]), which of the following AC specification values for tCH/tCL is supported by Note 30?
Which of the following is the AC spec value?

When FSCK > 50MHz, the value is 45% (=50%-5%)xPSCK.
tCH(Min) = (50%-10%)xPSCK : (40%)1200ns
tCL(Min) = (50%-10%)xPSCK : (40%)1200ns

Or does it mean that up to ±10% duty cycle is possible?
tCH(Min) = 10%xPSCK : (10%)300ns
tCL(Min) = 10%xPSCK : (10%)300ns