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Having Vcc = 3.3V, and Vio = 1.8V. What happens if I do not sequence Vcc and Vio?
The sequencing of Vcc and Vio in S29GL01GT datasheet conflicts with FPGA power sequencing, and causes all sorts of problems.
Thanks.
Show LessPlease see the attached document for a description of the issue being seen. Here is a summary:
We are interfacing it with STM32L476VGT Cube 4.26.1. Our firmware is running on STM32Cube_FW_L4_V1.12.0 (equivalent to 1.13.0 qspi). We have been able to successfully read the device ID (0x01 0x60 0x19), erase block (cant verify). Below are the routines, and the capture from our Saleae analyzer. I am looking for any guidance to help understand what the cypress part is looking for.
Show LessI always successfully used the S25FL064P in our design with Xilinx Spartan 6. Now the S25FL064P is obsolete and use the S25FL064L for the first time. Until now not successfully. I will list the log dump below. Bypass the ID check in iMPACT with XIL_IMPACT_SKIPIDCODECHECK is done. FLASH selection:
I hope that anyone can help me.
INFO:iMPACT - Current time: 28-3-2019 9:49:54
PROGRESS_START - Starting Operation.
'1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file C:/Xilinx/14.7/LabTools/LabTools/spartan6/data/xc6slx150_spi.cor.
'1': Downloading core...
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1100 1110 1100
INFO:iMPACT:2492 - '1': Completed downloading core to device.
'1': ID Check passed.
'1': ID Check passed.
'1': Erasing Device.
'1': Using Sector Erase.
'1': Erasing non-volatile quad-enable bit...
'1': Programming Flash.
'1': Reading device contents...
Failed at address, 1293056
'1': Verification Terminated
INFO:iMPACT - '1': Flash was not programmed successfully.
PROGRESS_END - End Operation.
Elapsed time = 278 sec.
Show LessDesign Overview
We are using 2- Spansion 16 bit parallel NOR flash S29GL512S11DHI010 for one of our application. The address and data lines from the PowerPC(MPC8548E) are connected to the flash through BUS TRANSCEIVERS. 32 bit data from powerPC to be stored into the flash. WE to the flash generated by PowerPC which is routed through a bus switch. And CE to the flash is directly connected from PowerPC.
Problem Statement
We could download the program to the RAM where as the issue is in downloading program to the flash. We are able to write/read the data into/from the flash through shell commands. Because of which we could read the Manufacturer id, device id, protection verification state and basic feature set information from the device. We are able to perform sector erase, where as chip erase, PPB lock bit read commands are not working.
Error Message
During flashing the chip we are getting an error "Could not unlock block 496 Flash programming terminated" as shown in the attachment.
Requirements of the Device
Power supply to all the devices are intact.
CE to the Flash is getting asserted before the WE is asserted and CE is de-asserted after WE is de-asserted.
Address and data are stabilized before CE & WE are asserted.
OE, RST and WP of the device are intact.
Hi,
I'm using the Texas Instruments TCM320C6748 DSP with the EMIF interface to communicate with the S29AL016J NOR flash.
The point is that when i erase a sector, then go into a while loop checking DQ7# until it goes high the sector gets properly erased.
But when i erase a sector, then do some other tasks with the DSP without checking the DQ7#...if (after a few seconds) i check the sector (by reading) i realize that some address are not properly erased and keeps the value previous to the erasing command. And even some times it seems to be properly erased but when writing there the DQ5# goes high saying the program operation have failed.
I can't find the problema and i'm quite confused, do you have any clue? Does it is mandatory to check DQ[7:0]# always after erasing?
If you need more information about whatever just tell me.
Thanks in advance,
Juan
Show LessPlanning to use S29AL016J70TFI020 16Mbit flash in one of our existing product. The existing chip used on the board need pin 15 to be connected to GND. We need the new flash to be a complete drop-in with no hardware change. Is grounding pin 15 (Ry/By#) going to affect the design and the S29 in terms of functionality and reliability?
Show LessI am looking for the BSDL file for the Spansion S29AL016J70TFI020 memory chip so we can reprogram it via the JTAG port. I would greatly appreciate assistance in this matter. Thank you.
Show LessHi, can you please cross this Altera/Intel part number to a Cypress P/N? EPCQ256SI16N
thanks