Nor Flash Forum Discussions

Hi there,

In the S29JL064J datasheet (Document Number: 002-00856 Rev. *I) on page 31 Figure 7 is a flow diagram for Sector Erase and Chip Erase operations:

Also, on page 35 there's the Figure 8. Data# Polling Algorithm:

From my previous discussions with Cypress technical support friends (thread: For NOR Flash, can RY/BY# (or Ready/Busy) pin replace Data Polling (and toggling bits) method? ), in my understanding, if I'm NOT doing erase suspend and only erase ONE SECTOR in a erase comand sequence, then polling DQ7 and DQ5 and run though the forthmentioned "Data# Polling Algorithm" shold be sufficient to know the result of a Sector Erase or Chip Erase operation: DQ7 tells me whether it's finished and DQ5 tells me whether it's successful or fail.

So, my questions are:

1, Am I correct in the above understanding?

2, In order to know the result of a Sector Erase or Chip Erase operation, is the above Figure 8 "Data# Polling Algorithm" flowchart sufficient? Is it OK that I DO NOT use the above Figure 7 "Erase Operations" flowchart?

3, Reversely, in order to know the result of a Sector/Chip Erase op, can I ONLY use Figure 7 "Erase Operations" flowchart and DO NOT use Figure 8 "Data# Polling Algorithm" flowchart?

4, As of the answers to the previous questions 1 thru 3, does these answers also apply to Cypress NOR devices including S29JL064H, S29JL064J, S29GL256P and S29gl01GT?

Hi there,

I'm currently using Spansion (which is now Cypress) S25FL032A in my design,

but I can't find its Verilog simulation model on the Cypress website.

Can anyone please give me any hint as of where to download it?

Thanks & Best Regards~

xieyl

2020.02.24

We have a new board with a Xilinx Artix-7 FPGA and a Cypress S25FL128S SPI flash.  I exported a SVF file from Vivado (v2019.2) to be used with our Goepel JTAG tools for programming the S25FL128S device.  This seems to work fine, I can program the SPI flash and the Artix will configure from the SPI flash.  A requirement has come down where I need to lock the bottom 1/4 of the device.  According to the S25FL128S data sheet, I need to set the TBPROT OTP bit in the configuration register to 1 in order to lock the bottom 1/4.  As soon as I do this I can no longer program the SPI flash with the SVF file.  I read the status register and the BP[2..0] bits still read 000, so they are not locked.  The funny thing is, I can still program the SPI flash using Vivado directly.  I can also bit bang data into the flash using boundary scan.  I'm not sure why the SVF file works before setting TBPROT but does not after setting TBPROT.  I also created an SVF file that only contains the erase command.  It seems to work regardless if the TBPROT is set or not.  I am wondering if the program function in the SVF is reading the configuration register and expecting to be 0?  I have reached out to Xilinx, but they have been slow to respond. I was wondering if anyone has seen something like this?

Can I get the Thermal Resistance Theta JC (top) Rjc, Theta JC (Bottom) Rjc , Theta JB (Rjb) & max junction temperature value for part# S25FL128LAGMFV013 ?

Hi there,

I'm currently thinking of migrating between two SPI Flash memory devices, S25FL032A and S25FL032P.

I know they're manufactured on different process technology nodes, and there are some differences in terms of AC timing characters.

However, due to some compatibility reasons, I still have to seek to use a same controller circuit to operate on both of them, but my controller design is relatively slow, and SCLK is not higher than 25MHz. So the question is:

If my SPI Flash controller operates at a low speed (SCLK is not higher than 25MHz), and I poll WIP to wait for enough time to allow program/erase operations to finish, then do I have confidence that my controller design works for both S25FL032A and S25FL032P?

Or, if my controller design works for S25FL032P, then can I say it will work for S25FL032A as well?

If my controller design works for S25FL032A, then can I say it will work for S25FL032P as well?

Thanks & Best Regards,

xieyl

2020.02.24

Hello Mam,

I find every where on Cypress support but i only get 19 pages pdf documents .

I want S70FL01GS Flash memory programming user manual for finding commands of Read/Write and erase.

Thanks & Regards.

Hi all,

I'm up to replacing our own flash file system with one that has more features.

I came across the Spansion FFS and would like to compare it to littleFs and SPIFFs.

I searched through a lot of the documents that I received about the Spansion FFS but could not find anything on the resources (program / data memory / RAM) that is being used.

I am using a TIVA Cortex-M4F processor and would like to access a S25FL127S by SPI (1 data wire, only).

Could someone give me a direction, please?

Best regards,

Rainer

Hi there,

About the DQ3 (Sector Erase Timer) bit, I have a few questions:

1, Based on my understanding of Cypress datasheets, DQ3 is used when we need to erase TWO OR MORE sectors in a single Sector Erase Command Sequence: after a "Sector Address + sector erase command 30h" has been input, we monitor DQ3; if DQ3=0, then it is OK to input additional "Sector Address+30h" to erase; if DQ3=1, then the erase op has begun and we should NOT input additional "Sector Address+30h".

Am I correct in this?

2, If in a Sector Erase Command Sequence we erase ONLY ONE sector, then we do NOT need to monitor DQ3.

If in a Sector Erase cmd sequence we erase TWO OR MORE sectors, but the timing between successive "Sector Address + sector erase command 30h"s are less than 50us (S29JL064H ds page 35) or less than tSEA (S29GL256P ds page 26), then we do NOT need to monitor DQ3.

Am I correct here?

3, In the following "Sector Erase Operation" flowchart (S29GL256P ds page 26), can I skip over or get rid of the "Poll DQ3, DQ3 = 1?" step ?

DQ7 and DQ5 can provide sufficient information about the progress & status (finished or not, success or failure) about Sector Erase; why bother polling DQ3 ?

4, In the above "Sector Erase Operation" flow chart, for its "Perform Write Operation Status Algorithm" step, can I use the following "Data# Polling Algorithm" flow chart in this step?

As far as I know, this "Data# Polling Algorithm" flow chart is applicable for all Cypress parallel NOR Flash devices, so I want to use it for compatibility across many device types I'm currently using (S29JL064H, S29JL064J, S29GL256P, S29GL01GT).

5, Chip Erase command sequence does NOT need to monitor DQ3, is this right?

Thanks for your attention, and Best Regards ! 🙂

xieyl

Feb 19, 2020.