Nor Flash Forum Discussions
Hi
There is a strange issue while using S25FL127S.
CPU is used to upgrade the data in flash, which is boot code.
If flash has been programmed with the right code already, then CPU can upgrade the data in the flash successfully.
However, if flash has been programmed with the wrong code already, then CPU cannot upgrade the flash successfully.
The failure shows CPU can erase flash successfully, then CPU programs and read it but find partial data is wrong.
Could you help find out the cause ? Thanks.
BR
Grace
Show LessWhen device is configured as word mode, #BYTE pin should be set to the logic high.
What should be the value of the pull-up resistor?
What are the recommended resistor values?
MPN
S29GL064S and
S29AS016J
Best Regards,
Naoaki Morimoto
Show LessHello, we are having some issues migrating from S29GL01GP to S29GL01GP.
We have a functional design that uses an FGPA with an S29GL01GT. Only the operations of simple reading, simple word writing and sector erase were implemented. To check the state of the algorithm only the RYBY signal was used.
We are having issues migrating this design to S29GL01GT10TFI010. We currently have two prototype PCBs and the problem is this: when a sector is deleted and then written, we cannot retrieve the data written in certain addresses (the read value is FFFF). These addresses are always the same, but they are different for each board. I attach a capture of the single word write, CH1: CE #, CH2: WE #, CH3: RY / BY, CH4: OE #. The first address is latched with the CE flank, and the data with the WE flanks. We wait for RYBY to go high before starting the next single word programming.
Are we missing something?, thanks.
Show LessHi Expert,
Please help clarify the CR1V QUAD bit behavior after CR2V QPI bit set to 1.
There are two descriptions in the datasheet as below:
1. From spec the CR1V description: "The QUAD bit must be set to one when using the Quad I/O Read, DDR Quad I/O Read, QPI mode (CR2V[6] = 1), and Read Quad ID commands."
2. From spec the CR2V description: "When this bit is set to QPI mode, the QUAD bit is also set to Quad mode (CR1V[1]=1). When this bit is cleared to legacy SPI mode, the QUAD bit is not affected."
So from the CR1V description, seems like the CR1V QUAD bit needs to be set '1' before set CR2V QPI bit to '1'.
From the CR2V description, seems like the CR1V QUAD bit needs to be set to '1' automatically when CR2V QPI bit set to '1'.
Which is the correct behavior for the CR1V QUAD bit after the CR2V QPI is set to '1' by WRAR (71h) command?
Thanks,
Mike
Show LessHi there,
I'm currently doing simulation with my NOR-controller design and S29JL064J Verilog simulation model. I experienced a strange behavior of DQ7 when I do Sector Erase simulation. A description of what I did is as follows.
1, The S29JL064J Verilog model is downloaded from Cypress official website; it's info is listed below:
Version: V1.1
Author: S.Petrovic
Date: 13 Nov 29
2, My simulation flow is as follows:
(1) Program 256 bytes of random data to NOR, starting from address = 00_1000h, and let address + 1 after each 16-bit-word program is finished successfully;
(2) Read 256 bytes from NOR, starting from address = 00_1000h, and I can see that these data are consistent with the data I programmed in step (1).
(3) Issue the Sector Erase command sequence to NOR, the address to be erased is 00_0000h.
(4) Read DQ7-DQ0 and go through the polling process.
3, What I saw in my simulation is:
Program and read seemed OK, which indicates that my simulation environment, my testbench, should be OK;
However, the first polling immediately after Sector Erase just gives me DQ7 = 1, which seems somewhat weird or strange.
4, Upon careful re-reading of S29JL064J datasheet, page 34 says: "During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or ..., Data# Polling produces a 1on DQ7."
So, in my expectations, the first polling should give me DQ7=0, but the S29JL064J simulation model seems to behave otherwise. My simulation waveform is shown below, all these signals are S29JL064J's port signals:
I mark my operations in yellow rectangles:
In the first yellow block, the NOR flash is fed with Sector Erase command sequence;
In the second yellow block, as you can see now RY/BY# (the RY signal near the bottom of the waveform) is low, which indicates the NOR device is busy doing internal erase operations, but polling DQ7 gives me 1, which is UNEXPECTED behavior.
5. To debug this, I delved a little bit deeper into the S29JL064J Verilog model. After grabing the model's FSM state into waveform, I can see that, with the input of Sector Erase command sequence, the FSM state machine's current_state signal (near the bottom of the above waveform) went through the following states:
RESET --> Z001 --> PREL_SETBWB --> C8 --> C8_Z001 --> C8_PREL --> SERS, and then it just stays in SERS state.
In the above timing diagram, while the S29JL064J's internal state machine actually stays in SERS(7'd17), the second yellow block the polling of DQ7 gives 1. Meanwhile, a signal "Status[7]" in the model just changes from 0 to 1 (last signal in the above waveform), which I guess should be the "1" that DQ7 captures.
From my amateurish understanding of the Verilog model, and by guessing from the "SERS" acronym, now the S29JL064J should be doing Sector ERaSe, but polling DQ7 gives me 1.
6. So, my question is, is there a possibility that the S29JL064J Verilog model might be giving wrong poll result at DQ7-DQ0 during Sector Erase?
Or, is my NOR controller issuing wrong commands to the S29JL064J Verilog simulation model?
消息编辑者为:yuanlu xie
消息编辑者为:yuanlu xie
Show LessHi there,
While I am using Cypress S29JL064H Verilog simulation model to do behavioral simulation, the sim log gives a weird timing Error:
# ** Error: ../vrf/S29jl064h/model/s29jl064h.v(1161): $hold( posedge OENeg:1000951 ns, CENeg:1000951 ns, 1 ns );
# Time: 1000951 ns Iteration: 1 Instance: /tb_norc/U_064H
Follow this error, line 1161 in <s29jl064h.v> is:
$hold (posedge OENeg, CENeg , thold_WENeg_OENeg, Viol);
And, the comments of "thold_WENeg_OENeg" says "tGHVL edge /".
In my simulation waveform, at the specified time (1000951 ns), the OE# rising edge and OE# rising occurs at exactly the same time. However, it seems the $hold requirement in the model requires that CE# rising edge should be later than posedge OE#, and seems this is defined by "tGHVL" parameter.
I went through the datasheets of S29JL064H, S29JL064J, S29GL256P and S29GL01GT, and there is NOT such an AC parameter called "tGHVL", and I CANNOT find any spec requiring that CE# rising edge should be later than posedge OE#.
Where can I find the definition of "tGHVL"?
Can I ignore the forthmentioned timing Error issued by the S29JL064H Verilog simulation model?
Or, should I modify my design to ensure that no timing error is reported?
Show LessI am using the S29JL064J and are seeing intermittent write behavior. We have three devices, two have undershoot on the WE and OE pins around -1.2V for ~ 20ns. For these two we see about a 90% and 10% write success. The third device does not have the undershoot and we see 100% write success.
My question is: Does the -2.0V undershoot for <20ns in the datasheet indicate that anything less the device will still function properly, or could our -1.2V undershoot be the cause of our write issues?
Show LessDear Cypress,
We are using the s25fl128 Flash memory to program the Artix-7 FPGA. We cant able to program or erase the Flash memory from FPGA. Please give your feedback.
When Data Lying b/w Sectors?
When we Write 8 bytes Data {01 01 01 01 01 01 01 01} on Address :- 0x0003FFFC & then Read 8 bytes data on Address :- 0x0003FFFC {01 01 01 01 FF FF FF FF}??
When Data Lying b/w 32kb Block?
When we Write 8 bytes Data {01 01 01 01 01 01 01 01} on Address :- 0x00007FFC & then Read 8 bytes data on Address :- 0x00007FFC {01 01 01 01 FF FF FF FF}??
Please response me as soon as possible.
Thank you.
Show LessCan you please share the Thermal Resistance Theta JC (Rjc), Theta JB (Rjb), Theta JA (Rja) & Maximum junction temperature value for part# S25FL128LAGNFV010 of WSON 5 x 6 package?
Thanks and Regards,
Jaiganesh, S
Show Less