Nor Flash Forum Discussions

Hello Team,

The Part "AM29F016D-90FI" got Obsoleted long back and it's bascially belong to Spansion which was acquired by Cypress semiconductor then now by Infineon. I wonder, whether Infineon could support anyhting similar to this?

Regards,

Suresh G 

HI:

    I would like to use write any register command (0x71) to configure one of configuration register( CFR2 volatile ) to command S25HL512 to enter qspi mode. But I could make this happen. Below is what I did, could you please help advice anything I did wrong? Thanks!

Step 1: send write enable command

step 2: write CFR2 volatile register: ox71  0x00  0x80  0x00 0x03 0x40

// setup command
s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
s_command.Instruction = 0x71;
s_command.AddressMode = QSPI_ADDRESS_1_LINE;
s_command.AddressSize = QSPI_ADDRESS_32_BITS;
s_command.Address = ( uint32_t )address;  // 0x800003
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
s_command.DataMode = QSPI_DATA_1_LINE;
s_command.DummyCycles = 0;
s_command.NbData = 1;
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;

// send command

//transmit address and register value

Hello,

We are facing a wierd issue with the S25HL512T device that we have. The device was working smoothly until one of our colleague power cycled it on boot and since then we believe the configuration got corrupted. 

We can write the configuration if we reset all the registers to zeros but cannot identify the device in QSPI mode. It does identify itself in QPI mode (1-4-4) but without the configured latency cycles or in SPI mode with the configured latency cycles. Also, we do not read 0x61 or 0x41 in STR1 register so the Safeboot process could not be followed.

We are writing the following values to the registers:

CFG1: 0x2

CFG2: 0xc8

CFG3: 0xd0
CFG4: 0x0

We read back:

CFG1: 0x2

CFG2: 0xd8

CFG3: 0xd2
CFG4: 0x0

STR1: 0x0

We don't know why the reserved pins are set even when we don't write to them. How do we recover this device to work in QSPI mode?

And what does it mean to read 0xff value from all the registers in QSPI mode?

We cannot provide any waveforms since it is not possible to access & probe the device.

Thank you

Hellop

We are currently utilizing the S25HL512T Flash in our project, and we have encountered a rather unusual problem that has been causing us some concern. When we initially flash the chip, everything appears to be functioning as expected. However, our issue arises when we attempt to perform an erase operation; it appears to cease functioning properly, rendering subsequent reflash attempts futile.

We have taken the liberty of thoroughly examining the LBROT Bits, all of which are consistently set to 000. As per our understanding, this configuration signifies that the chip is in an unprotected mode.

Given the circumstances, we kindly request your assistance in resolving this matter. Any insights, guidance, or troubleshooting steps you could provide would be greatly appreciated.

Thank you in advance for your prompt attention to this issue.

Sincerely,

HI,

   For our new product development, we plan to migrate from MT25QQ512 to S25HL512, could you help to let me know how to enter QSPI mode for S25HL512? Since I didn't find any command to enter QSPI mode, should I need configure CFR2 register(bit 6) to enter QSPI mode?

   Could you help to provide driver for Microsoft FileX and LevelX file system(FAT32)?

Thanks!

EVAL-S25FS256T SEMPER™Nano

https://www.infineon.com/dgdl/Infineon-SEMPER-S25SF256T_nano-memory-module-Quick-start-guide-GettingStarted-v01_00-JA.pdf?fileId=8ac78c8c8929aa4d0189912d399f5f7c

 when XTADD bit is 0 , 4READ(0x13) was readable and 4QOR(0x6C) was not readable.   Our test results is reasonable ?

Hello

I would like to confirm WRR command sequence of QUAD bit 0 or 1.

You can see  "When the configuration register QUAD bit CR[1] is 1, only the WRR command format with 16 data bits may be used." in page 84 of datasheet.

In case the configuration register QUAD bit CR[1] is 0, the WRR command format with both 8 data bits and 16 data bits may be used.

My understanding is correct ?

Best regards,

Kamijima

Do we need to set FREEZE bit  to "1"  by WRR command in parallel in case we want to write other bits (includes in OTP bits) in CR1 correctly ?     After the writing,  are data of OTP bits in CR1 fixed (no change)  permanently ?   

In case of FREEZE bit  "0" , are there any possibility OTP bits in CR1 may be variable ? 

Best regards,