Nor Flash Forum Discussions
Hello,
I am using the S25FL128SAG-NFI-001 WSON-8. i was using AT25DF641A flash and i have its implementation completed and running.
I have run into a bit of issue addressing the S25FL128SAG, i am struggling to find its cluster size and whether the block sizes are 4KB as in the AT25DF641A, or if they are both 4kb and 64kb depending on the sector being addressed.
I know that for the flash i am using the programming buffer is 256 bytes and the addressing is that 4kb sector at the bottom and 64 kb sector top. Can anyone help me have a clearer understanding of the differences in sectors, programming buffer and cluster size between the two devices.
Show LessI have downloaded SW from below link, facing issue while installing drivers I got below error.
Flash Explorer for FSK Programming Tool (cypress.com)
I am using below OS.
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Hello all,
I am writing to you again as I have another problem with the Spansion FFS example on the S256FL256LAGMFI Nor Flash. I now have the example with sample_spn_fs() working. If I start it one time and format the flash, I can write and read the example data - it works corrrectly.
However, when I start the example another time (even after MCU reset), sample_spn_fs() fails with IONFS_ERRNO because the data that it writes are not read back correctly. When I start the example another time or two times, ionFS_mount() returns IONFS_ENOFMT. That is the end and after this I must always start the formatting again. This procedure is not always the same as sometimes I get the error ENOFMT even right after the first run, as you can see from the following screenshot.
I know one thing, ionFS_mount() fails because it cannot find the boot sector where there should be written 0x55aa at the end. There are zeroes only even though ionFS_format() writes to it correctly. Another thing I want to mention is that decreasing the used size of the flash by lowering NUMBER_OF_ERASE_BLOCKS in Flash.h seems to almost fix the issue.
I had some problems with the stack size as the filesystem has some very large buffers defined in the functions, but I hopefully fixed those by setting stack size to 36 kilo. My idea is that this whole issue somehow related to write buffers not being flushed correctly to the flash, but I am not really sure.
I attach the whole sample_spn_fs.c file, but I almost did not change it from default. Also, I tried to get some output from the example with all calls to the slld_hal layer, but the output is fairly incomplete so I doubt it will be of any use for you.
Do you have any idea what could be reason for this? I would appreciate any input as I am, once again, stuck on this one.
Thanks and regards,
Karel
Show LessI need an idea of how long it would take (in an emergency) to erase the entire flash chip. Lets assume large 64KB blocks
How fast can a QSPI NOR Flash be erased?
Please provide examples and recommendations to achieve the fastest possible chip erase time using a 16Mb or larger QSPI NOR Flash.
Reference Does S29JL032J nor flash really takes 39 seconds for chip erase?
Greg
Show LessI'd like to test xSPI interface using NOR flash and I want to check those three interfaces
1) QSPI 2) Octal 3) Hyperbus
By the way, is there any solution to support those three or two interfaces at the same time on the single package?
I'm designing for a testing board putting on three kinds of interface components for them, but it seems like over using.
Show LessHello, I am having an issue with the S25FL128S flash memory.
On a couple pieces of our custom board imx6 based i'm not able read/write flash memory.
RDID (9Fh) command return correctly 01h 02h 18h 4Dh 01h 80h (figure 1) but read Status Register 1 (RDSR1 05h) return always value DFh (figure 2) that means:
WIP=1
WEL=1
BP0,1,2=1
Erase error E_ERR=0
Programming Error P_ERR=1
Status register write disable SRWD=1
Even a board power cycle don't change this behavior.
Can you help me to investigate?
Thanks
Figure 1
Figure 2
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Hello everyone,
I am currently working on electronic board, OMAPL138 which the only component the SPI FLASH NOR was changed from S25FL129 to S25FL256. It is said pin to pin compatible.
The SW environment on place is u-boot + linux.
u-boot was updated concerning flash configuration files.
We are compiling and creating an u-boot AIS file which is flashed on the MTD thanks to the TI script and else.
However, the omap does not boot on the new MTD S25FL256.
We added debug on both MTD .
Here is our results:
S25FL129:
The first trace of debugging appear after the serial_initialization in board_init_r function, called by start_s file.
We can see the idcode request (RDID 0x9F) defined by JEDEC and other data.
S25FL256:
There is no trace of debugging available.
Thanks to oscilloscope, we were able to analyse SPI transmission.
- In flash mode, we saw correct erase and written command.
- In operational mode, on master (OMAP) request for reading command, the slave (flash NOR) is answering byte per byte the first data from the AIS file.
So we supposed that the Flash NOR is correclty configured and accessible during flash operational.
But why it does not work? Why don't we see any JEDEC command? No serial debug trace?
Plus, what is the state of this remarks on forum? Could it be a problem for our configuration?
https://community.cypress.com/t5/Nor-Flash/Infineon-SPI-NOR-Flash-in-Upstream-Linux-and-U-Boot/m-p/126987/highlight/true#M2368
Here is the content of the patch file for the configuration of the NOR:
diff -Naur uboot-03.22.00.02/drivers/mtd/spi/spansion.c uboot-03.22.00.02-modified/drivers/mtd/spi/spansion.c
--- uboot-03.22.00.02/drivers/mtd/spi/spansion.c 2012-07-10 10:11:46.000000000 +0200
+++ uboot-03.22.00.02-modified/drivers/mtd/spi/spansion.c 2020-12-22 16:11:30.771700841 +0100
@@ -55,6 +55,11 @@
#define SPSN_EXT_ID_S25FL032P 0x4d00
#define SPSN_EXT_ID_S25FL129P 0x4d01
+#define SPSN_ID_S25FL256S 0x0219
+#define SPSN_ID_S25FL256L 0x6019
+#define SPSN_EXT_ID_S25FL256S 0x4d00
+#define SPSN_EXT_ID_S25FL256L 0x4d00
+
struct spansion_spi_flash_params {
u16 idcode1;
u16 idcode2;
@@ -129,6 +134,22 @@
.nr_sectors = 256,
.name = "S25FL129P_64K",
},
+ {
+ .idcode1 = SPSN_ID_S25FL256S,
+ .idcode2 = SPSN_EXT_ID_S25FL256S,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 256,
+ .name = "S25FL256S",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL256L,
+ .idcode2 = SPSN_EXT_ID_S25FL256L,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 256,
+ .name = "S25FL256L",
+ },
};
static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len)
I am facing 2 issues with the flash
1) As per my understanding of CFI Query addresses 21h and 25h (page 37 of datasheet), time needed to clear 1 block is 2^(10+4) ms. Is my understanding correct ? If not, what is the correct max timeout for block erase ? I am confused as this is a lot of time for erasing 64KB.
2) When I do sector erase, checking the status reveals DQ6 toggle but no DQ2 toggle but DQ3 set. As per my understanding, whenever DQ6 stops toggling,DQ2 should also stop toggling as DQ6 indicates suspend or complete. What can my current observation mean ?
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