I want to run a behavioral simulation of S29GL01GP.The secotor had been erased，and programed in word mode.But the data which be read from flash is 16'hXX2X.AS shown in the follow picture:

What‘s wrong in this timing sequence?

Hello,

I am looking for a cross for Adesto's AT25SF041-SSHD-B.

The absolute size can be larger. However, the SPI serial interface and register set have to be exactly the same.

Thank you!

Hi Cypress,

Are there Errata sheets for S25FL064LABNFI043 & CYW43903KUBGT? 

Try to check on your website but unable to found it.

NOR Flashに関する質問です。

該当製品は下記になります。

製品：S25FL256LAGNFM010

　　　S25FL256LAGNFB010

上記ICに下記機能が実装されているかどうかご教授ください。

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暗号化操作、セキュリティキー管理、ランダム番号生成などの機能を

部分的または完全に実装し、次のいずれかの機能を備えた統合回路チップ。

1. 電力、税務、公安、金融などの分野で特に使用される、

キー長が64ビットを超える対称暗号化アルゴリズム、

キー長が768ビット以上の整数因数分解に基づく非対称暗号化アルゴリズム、

またはキー長が128ビット以上の楕円曲線に基づく非対称暗号化アルゴリズムが

含まれています。

2. キー長が64ビットを超える対称暗号化アルゴリズム、

キー長が768ビット以上の整数因数分解に基づく非対称暗号化アルゴリズム、

またはキー長が楕円曲線に基づくキー長が128ビット以上の非対称暗号化アルゴリズムが

含まれています。

また、対称暗号化アルゴリズムの暗号化および復号化速度は10Gbps以上、

或は非対称暗号化アルゴリズムの署名速度は1秒あたり50,000回以上になっています。

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以上、宜しくお願いします。　伯東　二宮

Hi Team,

In our project we are using the SPI based NOR flash chip as a slave, whose ordering part number is S25FL256SAGMFI000. As mentioned in the data sheet the sectors are organized as per the Ordering Part Number i.e. in our case the sectors are A Hybrid of 32 * 4-KBsectors with all remaining sectors being 64KB sectors with 256B programming Buffer. But when we actually see in the Data sheet section 8.2 Flash Memory Array, we have found there are two ways that these sectors can be arranged, which are Bottom 4Kbyte or Top 4Kbyte. We wanted to know what are the factors which decides the organization of these sectors for this NOR flash chip.

Secondly, When 4P4E command sent for erasing the 4-KB sector, after the command the data sheet suggests to pass the 4byte address, in that case with this command, which of the addresses will get erased? What happens if the address passed is lies in the middle of the sector? whether it will erase 4KB size, continuing from that address or erase the 4KB sectors where the address lies?

Regards,

Shivam

Hi,

I am currently testing a S25FL512 flash. I am trying to test the read register function and sending a RDID command to the flash on SI (code 0x9F). However, I saw no response on SO and cannot read any data. (D0 to D3 are SCK, CS, SI and SO)

RDID

I then tried several other commands, including RDSR1 (05h) and RDCR (35h) nothing is appearing on SO signal.

RDCR

I even tried toggling FLASH_RST signal to warm reset the device serval times, but it didn't help.

Currently I have no clue why this happen. Could anyone give me some hints or advice to understand what is the issue? Could that due to Power on Reset of the device? 

P.S: My VCC and VIO are 3.3V, and VSS is at 0V. HOLD/RST/WP are grounded during the test.

Is there a time limit such as a timeout if there is a temporary waiting time during transmission / reception? If so, what would it behave? I couldn't find it in the datasheet.

In another device, there was a case where the SCL and SDA stuck at Low for a certain period of time (about 100ms) due to the SW processing of the master during I2C communication, and as a result, the slave device unintentionally timed out and the slave device reset. When I checked the specifications of the chip, the time-out specifications were listed, but it was not made with due consideration for SW.

I would like to check the specifications of the device to see if other devices are also considered.

Thanks,

Tetsuo

新規採用時の注意点として、Automatic ECC onでのご採用依頼をする為の

注意点資料をご案内頂けますか？

MPN:S70FL01GSAGMFI010

Flash 65nm MirrorBit Ecc onでの採用依頼A/N

こちらでしょうか？

https://www.cypress.com/file/301591/download