Nor Flash Forum Discussions
What are the possible problems when using NOR Flash beyond the operating temperature range to the low temperature side?
Please let me know because it doesn't matter in general terms.
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We have found the VERILOG model has issue.
Starting from "SFDP_array[16'h108E] = 8'hFF;", the SFDP array offset does not match with datasheet anymore.
Could you provide a correct VERILOG model which matches S70FS01GS datasheet?
Show LessHi All,
currently we are using following part # S25FL256SAGMFV011 in our design but due to stock not available we are looking for closest match part # which can replace the following part # S25FL256SAGMFV011
Show LessI am attempting to use the write buffer programming process to write all 256 16-bit words with the same constant value as part of a device sanitization process. I know the command sequence to run the write to buffer process but I have not had success in simulation. The unlock and setting commands are issued correctly, as is the following writes to all 256 buffers, but the ready signal goes low halfway through writing to the buffers and stays low indefinitely. Attached are three waveform screengrabs of what I am doing and seeing in simulation.
Picture1: Two unlock commands, issue "write to buffer" command at sector address 00, issue number of locations (255) at sector address 00, start loading address/data pairs
Picture2: Ready signal going low halfway through buffer address/data writes
Picture3: Finish buffer address/data writes and issue "write buffer program confirm" command at sector address 00
Show LessHello Everyone:
We are not able to set 'WEL' bit in Status Register 1, or even read back what is written in Memory. We are using a FPGA to interface with Serial Flash S25FL256S... . Below is the sequence of operations.
- Power up
- Wait for Tpu of 300us
- Read JEDC ID (Instruction 0x1F). Correct data is read back.
- Issue WREN (Instruction 0x6)
- Issue Erase Flash Array (Instruction 0x20, address bits[23:0] = 0x0)
- Wait for 11 seconds
- Issue Status register read (RDSR Instruction 0x05), reads back 0x0. Expect WEL (bit 1 to be set since WREN was issued).
- Issue Page Program (PP, Instruction 0x2, address[23:0] = 0x0, 4 Bytes of data).
- Wait for 2 ms (for page program to complete).
- Read Status 1 register, reads back 0x0.
- Read Flash Array (Instruction, 0xB, address [23:0] = 0x0, ), reads back 0xFF all bytes. So data could not be stored.
I am attaching some waveforms showing the operations. The file names of waveforms indicate the type of operation being performed. These waveforms are from Xilinx Vivado ILA. The signal names are mapped as below.
SCK: jb_cp_mem_clk_OBUF
CS#: cp_pMem_csN_OBUF
IO[3:0]: cp_mem_in_OBUF[3:0]
Below is some information about the operations shown in the waveforms.
1) Read JED ID & Issue WREN.jpg: This file shows that reading of JEDEC ID is working. After reading the ID, we are issuing 'WREN' Instruction to set the 'WEL' bit.
2) Erase Flash Array (P4E).jpg: Before writing we are erasing the sector at address 0x0.
3) Read Status register 1, RDSR1 .jpg: Reading Status Register 1, read back data is 0x0.
4) Page Program & Read Status Register.jpg: Write data to memory and read Status Register 1, read back data is still 0x0, WIP bit not set.
5) Read Status Register & Read Flash Array.jpg: Read status register and read data from memory. Status register is still 0x0 and data read from memory is all 0xFF. Four bytes were written and four bytes read back.
Did we miss anything from the datasheet? Are we doing something incorrectly? Please help!
Thank you so much.
Best regards,
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We already qualified S25FL512SDSMFB010 (Cypress part) in our boards however, I found some failure recently and also found there is the a Spansion Mark on the failed parts. So what is the difference?
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Is there any equal 4KB erase sector SPI Nor Flash solution in Infineon portfolios?
I checked in Semper series and S25FL/FS, S70FL/FS, all of them are uniform 256KB erase sector, or hybird sector architechture(4KB in top/bottom, rest is 256KB).
Need your confirmation, thanks
Show LessHi All,
We are using OSPI NOR Flash S28HS512TGABHM013 in our product. It would be great if you can share compatible driver for Linux-5.10.35 version.
Hardware Platform: i.MX8QM
Best Regards
Babu A
Show LessHello everybody!
Recently I was doing some hacky/fancy tests of flash chip behavior between different manufacturers when it is used not *exactly* how it was intended 😉 I was changing configuration of external memory controller in my MCU to drive WE# line low or high during reading operation (used for example for chips with byte lane selection etc.) and I've encountered something strange which I couldn't find in the S29AL016J datasheet.
In other flash chip manufacturers (pin-to-pin comp. + same timings and control) when I try to perform read operation ("uint16_t test = *(uint16_t*)(FLASH_BASE);") everything works correctly, i.e. data is exposed on data lines if WE# line is driven high, and data lines are kept low if WE# line is driven low.
In S29AL016J it doesn't matter if MCU drives WE# line low or high during reading, chip drives data lines anyway!
It looks like some flash chip's internal state machine checks if address set on address lines is "special" one (0x555 etc.) and if not, it executes read operation and exposes data on data lines.
Could anybody confirm it?
Some snippet code looks like that:
//set EMC to drive WE# line low during reading
//EMC_cfg_we(FALSE);
//set EMC to drive WE# line high during reading
EMC_cfg_we(TRUE);
while(1)
{
uint8_t test = ( *( Uint16 * )(0x80000000L)) & 0xFF;
uart_putc(test);
delay_ms(500);
}
I have few identical PCBs with same MCU, only flash chip is different.
I would really appreciate for any explanation!
BR
Adam
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