The latest datasheet for the S25FS256T 256Mb SEMPER™ Nano Flash has the description below at the end of Section 5.6. Does anyone have a clear definition of what "bit-walking" means in this context?
Device will do 1-bit error correction and 2-bit error detection. The 16-byte unit data requires a 9-bit Error
Correction Code for 2-bit error detection. Any 1-bit error in a data unit is corrected and any 2-bit error is detected
and reported. Byte-programming, bit-walking, or multiple program operations to the same ECC data unit
(without an erase) are not allowed and inputted data will not be programmed correctly.
We have planned to use the NOR flash (S70GL02GS12FHIV20) for our image storage application.
In the ordering information of the datasheet, 02 indicates that Vcc=2.7V to 3.6V , Lower address sector protected.
1) what does this sector protection implies? Does this mean that during powered on, lower address of all the sectors are protected?
2) what is higher or lower address sector protection ? what is the functionality? Kindly brief them.
I am using Parallel NOR Flash memory part : S70GL02GS12FHIV20 in our application. From datasheet, we can able to understand that, V2 - Corresponds to lowest address sector protected. Below are my query:
1. How much memory size does it protect? - Does it protect entire 1Gb or few bits. Please confirm
2. What will be maximum PCB routing length for address lines , data lines and Control signals lines?Show Less
What are the thermal resistances junction-to-ambient, junction-to-case, junction-to-board, etc. of S29PL127J70BFI040 ?
What is absolute maximum junction temperature ?
I am currently trying to download flash (both sof and elf)file to EPCS (S25FL128SAGMFi011) on DE-1 SoC (Cyclone V 5CSEMA5F31C6).
By using the method in AN98558, I have succeeded downloading everything to my FPGA board and the command shell displays everything correctly. But it can only be proceeded once.
After the first time, I power off and on the FPGA board. Then I will get this error in Nios2 command shell: Error(209014): CONF_DONE pin failed to go high in device 2. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND.
I am a software engineer and I don't find any settings on Quartus that can set these pins. My questions are:
1.How can I reprogram the EPCS again via Nios2 command shell?
2. Do I need to use any external circuits or devices to actually set these pins to GND?
I am using Quartus 18.1 on windows 11 and the methods for Quartus 17 mentioned in AN98558 works perfect for me. I have attached the pictures of FPGA, S25FL128SAGMFi011 and the error message below.
Any suggestion will be appreciated. Thank you.Show Less
The S70GL02GS has two sector protection models.
Highest address protection model ,lowest address protection model
Could you please tell us each application .
Yutaka ShimoedaShow Less
I need a guru to help me here. We bought a bunch of Cypress flash memories S34ML04G204BHI01 and we also have some Cypress S34ML04G204BHI003 from the past. I couldn't find the S34ML04G204BHI003 online anymore, I am assuming it's end of life. My question is what the difference is between S34ML04G204BHI01 and S34ML04G204BHI003? Is there any firmware change required from S34ML04G204BHI003 to S34ML04G204BHI01 at all?Show Less
Can only write28 bytes in one write 24bit address quad command.
Looping can write a large size via the small chunks
The device appears to be locked in quad mode ?
Is there ANY jedec sequences that should work
Here a synopsys controller is sending commands erase/ get device id etc all work
Perhaps some "trick" bit must be set.
The mbed os code targeting cypress appears to simply dump data to the fifo.
Is there any "kit" from infineon to easy see the chip do ALL the tricks ?
Thanks for any reply !