Nor Flash Forum Discussions
I am wondering if it is OK to set the minimum time from the negation of chip selection to the assertion of chip selection at 20ns for read instructions, and at 50ns for implicit instructions other than read, etc. I am wondering if it is OK to refer to tcs.Show Less
Looking at the S25HS Family of QSPI, I see the Output Valid (Tv) for the HS-T ranges from 2-6nS. Is the max value entirely dependent on capacitive loading of the outputs? If not how else can I ensure I'm operating closer to 2nS than 6?
I am using SPI Serial Flash Memory, 512Mbit, SO16 package in one of my design. I am finding many chips getting faulty in 5 to 6 months of operation in field as all access fail post that.
On analyzing one of the field return card. I am able to read device ID of this part but starting few sectors read/ write is not consistent and finding number of places data read not matching with data written.
We tried to reprogram multiple times but data integrity is not there in various sectors belong to first bank.
Device ID is getting detected by firmware always. Just printing one uboot print of processor log.
Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB
Since data is not consistent in various sectors and we are using this as processor boot memory, so processor gets stuck during bootup.
We are using mostly first bank (16MB) location only for processor uboot. On faulty chip, we found read/write access to locations 4MB onwards (all 3 banks except first) is ok. Since it is processor boot memory, so would be read just once during processor boot and write only if any image upgrade needed which is rare.
Datasheet mentions 100,000 Program-Erase Cycles on any sector typical. These sites are not having power backup and almost gets power cycle on daily basis but it does not explain endurance of sectors.
We noticed that part S25FL512SAGMFIR11 used is with VIO option but this pin is kept NC in our design. Measured voltage at this pin is 3.3V but dips to 2.5V while doing any access in working chips too. Below is the measurement done in one of the working board.
Host is operating at 3.3V IO level which is the same supply of flash VCC.
I am trying to change the "Infineon Endurance Flex architecture Selection Register" of S25HL512. for example, After doing WRENB_0_0(0x06), 0x71,0x00,0x00,0x50,0xFD in WRARG_C_1 "Infineon Endurance Flex architecture Selection" There is no change in "Register". Do I need any other commands?
15. It is required that the high endurance data and long data retention
regions are configured at the time the device is first powered-up by the
Once configured, they can never be changed again
There is a description. This doesn't mean the one time you turn on the device after leaving the factory, right?
This means that it can only be done once after the device is powered on, so if you haven't rewritten it, you can understand that it can be done at any time, right?
I am using S25FS512SAGNFI011 Nor Flash for the FPGA Arria 10 configuration. I generated .jic file from .sof file as described in the document AN229767 of Infineon. I get the successful result on the tool when I load the file to the flash, but the FPGA does not boot up after power cycle.
My settings for the generating the file are below:
I'll be glad if you can help me.
The S29AL008J70BFI010 datasheet lists the sector trace time as "10s",
The S29AL008J70BFI010 datasheet lists a maximum sector trace time of 10s.
I understand from the above description that if it takes more than 10 seconds to execute a sector trace, it is considered to be abnormal, Is this correct?