Nor Flash Forum Discussions

    Hi,

We are working on S70GL02GT11FHV010 NOR- Flash , in that we are tried to program the buffer ( i.e write to buffer , buffer to Flash using the commands)  mentioned in the data sheet(page no-54) but we are failed to getting the correct answer.

Kindly help me to resolve this issue.

Thank you

Hello Support,

My device model is FS01GSAIF01, and I am using the WRAR command to change the QUAD_NV(Bit1) of CR1NV, it is found that the bit is always 0; I don't know where the problem is. My workflow is:

1. Send the 06h (WREN) command to enable write enable
2. Send the B7h (4BAM) command to enter the four byte address mode
3. Send the 71h (WRAR) command for writing registers
4. Send register address 0x00000002
5. Send data to be written 0x02

Additionally, the controller I am using is cadence Flash QSPI Controller IP.Is this the correct operation?

Best Regards

Hi, 

Raising this new ticket as previous one "512Mb flash S25FL512SAGMFI013 failure" closed and not able to reply for the post.

Background:

SPI Serial Flash Memory S25FL512SAGMFIR11, 512Mbit, SO16 package is going for failure within 6 months to 1 year of time period.

An update from my originally reported problem. 

On analyzing one of the field return card. I am able to read device ID of this part but starting few sectors read/ write is not consistent and finding number of places data read not matching with data written.

We tried to reprogram multiple times but data integrity is not there in various sectors belong to first bank.

Device ID is getting detected by firmware always. Just printing one uboot print of processor log.

Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB

Since data is not consistent in various sectors and we are using this as processor boot memory, so processor gets stuck during bootup.

We are using  mostly first bank (16MB) location only for processor uboot. On faulty chip, we found read/write access to locations 4MB onwards (all 3 banks except first) is ok. Since it is processor boot memory, so would be read just once during processor boot and write only if any image upgrade needed. (Happened 4-5 times only)

Datasheet mentions 100,000 Program-Erase Cycles on any sector typical. These sites are not having power backup and almost gets power cycle on daily basis but it does not explain endurance of sectors.

Please take up this on high priority. What is the external operating factor explains this issue.

Thanks

Anurag

Hi all,

our board is equipped with a S70GL02GS 2Gbit NOR FLASH and a NXP T2080 processor.

We address two 256Mbyte physical banks (in this description I report the physical addresses we use ) divided in 4 128Mbyte logical banks connected to CS0 and CS2 as depicted in the following scheme:

CS2        Bank0 0xe0000000         -----------------------------------------------

                                                                              128MByte

               Bank1 0xe8000000         -----------------------------------------------

                                                                              128MByte

CS0        Bank0 0xF0000000         -----------------------------------------------

                                                                              128MByte

               Bank1 0xF8000000         -----------------------------------------------

                                                                              128Mbyte

                                        ----------------------------------------------- 0xffffffff (end of addressing)

On each bank we mount a filesystem (TFF0,TFF1,TFF2,TFFS3).

For CS0 we have TFF0 and TFF1, and each file system has a 64MByte dimension because these banks contain the reset word and the BootRom.

Our board boots (as written in the HW configuration of the T2080) from CS0 (thus from now on we will ignore CS2).

BootRom is written in the NOR memory starting from 0xfff00100 physical address and if we dump here we find the correct BootRom.

Here I attach the screenshot of the non corrupted memory:

see FIG1_not corrupted_NOR

When everything goes OK the micro T2080 boots correctly and the first instruction is found at the end of the bootRom. Thus at the address 0xfffffffC we find 0x4bff804.
On the other hand when the NOR flash is corrupted, the same part of the memory (size 131Kbyte = 0x20000) from address 0xFFFE0000 to address 0xFFFFFFFF, is erased (0xFFFF values written) as depicted in the following 

see FIG2_corrupted_NOR

This fact (the deletion of the correct values in the physical address range 0xFFFE0000 + 0xFFFFFFFF of the NOR FLASH obtained by writing 0xFFFF in that address range) happens often.
Could be a spurious signal issue?
Could be a spurious signal on the reset input of the flash?
Coul be something else?

Thank you for your answers.
Massimo

Hi,

We have the S25FL064LABNFI010 in one of our designs, and cannot program it (previously this was done by the CEM, but they "forgot" for this batch...)

I'm attempting to use an FTDI C232HM-DDHSL-0 cable onto our board (connecting /CS, CLK, IO_0, IO_1 and GND), and the linux flashrom software to write in the supplied (and proven) .bin file. This is a copy of the setup they have, so it 'should' be possible.

I think that we may not be calling the flashrom program with the correct parameters, but (as always with linux) things don't ever actually work and the user is left to guess why not. 

Has anyone used this combination and can help me work out the right settings please?

Thanks,

Colin

Hi,

We are using S29GL064S NOR FLASH of Model 03. We are using 16 bit address mode. As per datasheet, Block 127 to 134 are 8K/4K. I wanted to erase, read and write the this 8/4K blocks. Read and write operation are working fine in this block. But when i give erase command, its erasing complete 127 to 134 block instead of erasing only 127th Block.

Can you help me is this the expected behavior or missing something?

Thanks in advance.

Hello everyone,

I am currently using an s25fl256s flash memory, but when I try accessing it (using an SPI master on an Artix7 FPGA) the first read access has a delay of 19 clock cycle (more or less) and afterward the data is received correctly, does anyone know what causes the delay on the first read access ? According to the datasheet (Figure 67 Read command sequence (3-byte address, 03h [ExtAdd = 0])) there should be no delays : https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17