Nor Flash Forum Discussions

We are planning to use Erase Suspend and Resume operations during Sector Erase in S29GL032N NOR Flash.
We want to know if there is data available for how much one Erase Suspend and Resume operation will impact on the Sector Erase time (min and max).

Also want to know the device Reliability due to frequent Suspend/Resume operations during Sector Erase.

Regards,

Anil Patil

I have one doubt regarding S25FL256SAGMFI013 NOR Flash. I am interfacing this with Virtex 7 FPGA. Let me know the supply voltage of SCK pin if I am tie VIO pin to 1.8V? 

We are planning to use S29JL032J70TFI01. For this device we will need Sector Protect and Unprotect support for In-System programming. We want to know more on the Sector Protect/Unprotect support with this device. After reading the datasheet it looks like we will need to provide VID voltage of around 12V in Hardware. Could you also share us the recommended Hardware implementation for providing VID when required and making it back to normal as required?

Thanks and Regards,
Anil Patil

hi, 

I am working on S25Fl512, The default mode is SPI and dual mode, which is working properly.

but in case i want to use QSPI mode, I could not do this. I think my sequence is wrong, I am posting the function to enter in QSPI mode, please correct me where i am wrong.

int32_t QSPI_EnterQPIMode(QSPI_HandleTypeDef *hqspi)
{
  QSPI_CommandTypeDef s_command;
  uint8_t data[] = {0x02, 0x02};
  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
  s_command.Instruction       = 0x01;//MT25TL01G_ENTER_QUAD_CMD;
  s_command.AddressMode       = QSPI_ADDRESS_NONE;
  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
  s_command.DataMode          = QSPI_DATA_NONE;
  s_command.DummyCycles       = 0;
  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;


  if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
  {
	  return QSPI_ERROR;
  }

  /* Configure the command */
  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
	  return QSPI_ERROR;
  }

  /* Transmission of the data */
  if (HAL_QSPI_Transmit(&QSPIHandle, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
	  return QSPI_ERROR;
  }

  /* Configure automatic polling mode to wait for end of program */
  if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
  {
	  return QSPI_ERROR;
  }
  return QSPI_OK;
}

uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
{
  QSPI_CommandTypeDef s_command;
  /* Initialize the read command */
  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
  s_command.Instruction       = 0x6B;//QUAD_OUT_FAST_READ_CMD; /* same value on both memory types */  // for single line 0x03; dual line 0x3B
  s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
  s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
  s_command.Address           = ReadAddr;
  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
  s_command.DataMode          = QSPI_DATA_4_LINES;
  s_command.DummyCycles       = 0x08;//QspiInfo.DummyCyclesRead;                                     //for single line 0x00;
  s_command.NbData            = Size;
  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;

  /* Configure the command */
  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    return QSPI_ERROR;
  }

  /* Set S# timing for Read command: Min 20ns for N25Q512A memory and 10ns for S25FL512S memory */
  MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_2_CYCLE);

  /* Reception of the data */
  if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    return QSPI_ERROR;
  }

  /* Restore S# timing for nonRead commands */
  MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_5_CYCLE);

  return QSPI_OK;
}

/**
  * @brief  Writes an amount of data to the QSPI memory.
  * @param  pData: Pointer to data to be written
  * @param  WriteAddr: Write start address
  * @param  Size: Size of data to write
  * @retval QSPI memory status
  */
uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
{
  QSPI_EnterQPIMode(&QSPIHandle);
  QSPI_CommandTypeDef s_command;
  uint32_t end_addr, current_size, current_addr;

  /* Calculation of the size between the write address and the end of the page */
  current_size = QspiInfo.ProgPageSize - (WriteAddr % (QspiInfo.ProgPageSize));

  /* Check if the size of the data is less than the remaining place in the page */
  if (current_size > Size)
  {
    current_size = Size;
  }

  /* Initialize the adress variables */
  current_addr = WriteAddr;
  end_addr = WriteAddr + Size;

  /* Initialize the program command */
  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
  s_command.Instruction       = 0x32;//QUAD_IN_FAST_PROG_CMD; /* same value on both memory types */  // single line command 0x02
  s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
  s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
  s_command.DataMode          = QSPI_DATA_4_LINES;
  s_command.DummyCycles       = 0;
  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;

  /* Perform the write page by page */
  do
  {
    s_command.Address = current_addr;
    s_command.NbData  = current_size;

    /* Enable write operations */
    if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
    {
      return QSPI_ERROR;
    }

    /* Configure the command */
    if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
    {
      return QSPI_ERROR;
    }

    /* Transmission of the data */
    if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
    {
      return QSPI_ERROR;
    }

    /* Configure automatic polling mode to wait for end of program */
    if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
    {
      return QSPI_ERROR;
    }

    /* Update the address and size variables for next page programming */
    current_addr += current_size;
    pData += current_size;
    current_size = ((current_addr + QspiInfo.ProgPageSize) > end_addr) ? (end_addr - current_addr) : QspiInfo.ProgPageSize;
  } while (current_addr < end_addr);

  return QSPI_OK;
}

 controller is STM32H743,

please suggest me sequence, or else if any example let me konw.

thanking you

Hi All,

NOR Flash S29JL032J70TFI01 we are trying to incorporate in our design. We have been looking for Sector Protect and Unprotect support within device through In-System programming. Datasheet for the same mentions RESET# pin need 12V during protect/unprotect operation. We are not able to find additional information on it. From Datasheet Specs looks like we need VID voltage of around 12V in Hardware. Need to know what Hardware logic to get implement to achieve this. If you can share some reference Hardware implementation logic on this

I am working in the railway market. We have a very old safety product that is equipped with 28F010 type NOR flash memories. We would like to resurrect this board for a customer but since the board is safety we are trying to avoid a respin (if possible).

The part was in PLCC-32 package (soldered) : SPANSION/AMD/CYPRESS AM28F010-90JI    (obsoleted in december 2005)

28F series NOR flash components were 5V-supplied but also required an additional 12V supply on VPP pin.
My understanding is that the 29F series are direct remplacement solutions (often pin-to-pin compatible) where the VPP pin is N.C. since those chips will work with 5V only. Am I right?

Yet I am wondering if it is really that simple. I was expecting to find a migration guide along with the PDN of this component. But not only the PDN won't suggest a direct replacement part but also the topic seems so complicated that the recommendation is to reach for the local representative of the brand :

AMD is obsoleting the Am28F010A, Am28F010, Am28F020A and Am28F020. Limited Fab capacity
and the continual migration of our customers to 5Volt and 3Volt Flash have necessitated the
obsolescence of these devices.  Please contact your sales representative for information regarding the migration
from 12V to 5V or 3V devices.

Is there an official migration guide for these old products?

Otherwise is there other know differences between 28F and 29F products aside from the VPP pin ?

I guess that 20 years ago this was a basic knowledge in the EE world. But today I am struggling to find a good article on this topic.

Hello, I'm wondering if it's possible to use the S25FL128L-Series ICs as an active-serial configuration device for a Cyclone V FPGA. I found the AN200498 Application Note that gives instructions for usage with the S25FL128S series, which appears to be the 16-SOP equivalent of the 8-SOP S25FL128L.

The main difference appears to the the pinouts, and Reset# being tied with SIO3. If I were to disable the Reset # support via the non-volatile configuration register, would I be able to use it in the same way?

Thanks.

Hello,

Please let me know the Month/Year of the date code '136BB242'.

Part number: S29GL128P90FFIR10

Rot number: GU43980000

Best regards,

Ayuko Ishizaki