Nor Flash Forum Discussions
Hi
By default in There is no option to set DUAL SDR (1s-2s-2s)configuration in S25HS01GT model.
Could you please tell me how to configure Dual SDR mode .
Thanks
Suresh
Show Less
Dear Team
I am using Parallel NOR Flash memory part : S70GL02GS12FHIV20 in our application. we are doing the sector erase before writing a data. Below are my query:
1. we are continuously erasing the 512 sectors one by one, by checking the RD/BY# pin status. we have noticed that same random Sector were not erased properly. This sector address is not fixed address, it is changing randomly. Please confirm the possible reason.
Based on which status either RD/BY# pin status or Status register, Sector erase need to progress. Please confirm.
Also, recommend the suitable methods to use before doing the Sector erase.
Show LessI like to adapt the above device on AN229767 to configure a Intel Cylcone 10-GX FPGA. In table 30, page 59 a list of registers is given. I am missing the actual address to be used for each register when using a WRAR command or even just reading by Read Status Register command. I assume but can not find evidence that the address is:
0: Status Register 1
1: Status Register 2
2: Configuration Register 1
3: Configuration Register 2
4: Configuration Register 3
5: Configuration Register 4
Hello friend
I am using S25FL256L QSPI flash on an Intel Tornado VE FPGA and have scripted for flash programming via JTAG mode in Quartus Programmer. For read ID autodetected as QSPI 256MB flash, the blank check process completed successfully, but failed at the program stage.
Programming fails at about 33% and programming completes. The following error is displayed:
Error (20064): Error status: Status 2 register read returned 0xFF. Does not match the expected data (0x00). Error (19117): Programming failed on flash 1 at address 0X00BB0100. Error (209012): The operation failed."
When reading the status 1 (0x05) and status 2 registers (0x07), the value of address 0x00BB0100 is returned as 0XFF. To write a page in 4-byte addressing mode, use the 0x12 command. For addresses before 0x00BB0100, the error does not occur because the read status 1 register (0x05) and the status 2 register (0x07) were added.
Can you tell me the cause of this error CAN CAN .
Thank you
Sneharu B.
Show LessHi,
I bought Nor Flash (S25FL128SAGMFI013) from market which falled under Cypress. However, the body marking is SPANSION.
Can help to provide me with any official statement or letter to confirm the merger between Spansion & Cypress before Infineon acquisition?
Show LessIs there a problem if one sector is being erased while another sector (not being erased) is being
Is there any problem if a sector is being erased while another sector (not being erased) is being read?
Are there any restrictions on accessing FLASH while erasing a sector?
I have a new design that is using the Cyclone 10 GX INTEL FPGA and I found in the IINTEL documentation that the S25FL256S FLASH Memory is directly supported. There is no selection in the Quartus Prime Pro software other than following their flowchart programming. Does someone have the exact entries for the flowchart programming or is there a patch to add to Quartus to directly create a .jic and .rpd file that the Quartus programming using the USB ByteBlaster will work?
Thanks.
Glenn
Show Lesshi sir, we 've just bought S29GL128S90TFI020 from franchise channel,but found out having broken wire bond issue,
could you pls check help to check if normal? can use?how it happened,thanks
Show LessWe are using S25FLS QSPI flash on our board. Some of the ICs are responding on single data line like SPI flash and some ICs are responding on 4 data lines.
We are unable to understand the reason. It is supposed to be QSPI flash by default.
Show Less