Nor Flash Forum Discussions

I'm currently reviewing the S25FL512S to be used as a QSPI device. Looking through the data sheet I can see a rise and fall time slew rate specified for the clock. Are there any rise and fall time specifications for any of the data lines or the chip select line?  Under the AC test measurement conditions I can see a maximum Input Rise and Fall time of 2.4 ns listed, but that's about all I can find.

Hello, 

We are developing battery operated device with u-blox NORA-B106-10B (ESP32-S3) module as a MCU. Due to large flash (64 Mbit) project requirement, we have selected Infenion S25FL064L (S25FL064LABMFI013) flash connected over SPI interface. 

As per ESP-IDF docuement, (esp_deep_sleep_start()) function will force power down flash regardless of user configuration. 

As per our testing observation with ESP32-S3-WROOM-1 (It has external 64Mbit SPI flash memory. Sorry, Not sure about Flash memory vendor part number), we could put SPI flash memory in sleep mode and takes less than 1 mA.

Same test we have also performed with u-blox NORA-B106-10B  and Infenion S25FL064L (S25FL064LABMFI013) flash memory in our prototype hardware. It takes around 10-12 mA current consumption when MCU in sleep mode (lowest power mode of ESP32-S3). It means, S25FL064L couldn't switch to power down mode when MCU in sleep mode.

Looking forward for your response. Thanks in advance.

Hi,

Is this part (S34ML02G200BHI003) in Production/NRND/EOL?

Regards

Kapil

Hi 

What does Mode “2” mean for Quad I/O Read in Latency codes of Table 24 ?

Please find attachment file.

Does that mean the “number of clocks” of mode bits ?

Additionally the mode bits should be equal to Axh ?

Best regards,

• We are interfacing Parallel NOR Flash (S29GL256P)  with our MCU. It should be usable in both 8 & 16 bit modes
• MCU address lines: M_A23 - M_A0 (M_A0 is always LSB)
• NOR Flash address lines: A23 - A0 (16 bits)  + A-1 (LSB for 8-bit mode)
• Connection for 16 bit mode: M_A0 to A0
• Connection for 8-bit mode: M_A0 to A-1

1. Is the above understanding correct?

2. Depending on 8/16 bit mode the MCU lines connect to different pins. Does this shift in address lines need to handled by software?

3. In 8-bit mode, the MCU M_A0 pin connects to NOR A-1 pin. Is this understanding correct? Or can we leave DQ15/A-1 just connected to the data line (Not connected to any address line)?

We require junction temperature, Thermal resistance and Operating Ambient Temperature details of the below products :

1.S25FL128S

2.S29GL01GT10DHI020

3.S29GL256S11DHIV20

I am trying to work the S25FL256L flash with the qspi interface of STM32F777ZITx on a custom board and I want to bring up the external flash.

I was able to call the memory mapping API and resulting into something like that which leads me to the conclusion that the memory was not initialized correctly.

The LLD driver assumes a SPI interface interface. Is there some code lying around with leverages the QSPI HAL interface of the stm32. Adapting the LLD driver to the stm32 seems to be tall order or is it ?

Can someone clarify whether this driver can work with the my chip that I mentioned please :- https://github.com/STMicroelectronics/stm32-s25fl128s

Hello,

I have used red arrow to highlight the symbol long X shaped lines. What is the meaning for this X shaped lines? Can I get some document to explain the top marking for part number S29PL032J70BFI120 ?

We want to protect the read operation from Flash memory, only  Authentic source can read , write and erase the flash memory.

How can we do so.

Regards,

abhisheknaik@simen.com

Abhishek Naik

I am having trouble erasing a S29GL256P.  We have it working on a few boards. We are doing prototype and have the chip on its on board and jumpered to the main board.  We have had two units not work when we added connections for a logic analyzer. I believe the logic is ok since I got other boards to erase and program. I am wondering if the status register data can indicate the issue.

I created a simple case were I erase sector 0 (0x00 0000). I have attached screen shots. 

Here is a summary of what I read from the status register. The first read is about 1 us after the erase command. Below is the time stamp relative to the first read and the status register data.

@ T = 0 us     0x0008 - DQ3 went high very fast.  tsea is a max of 50 us. What is the min?

@ T = 1 us     0x004C

@ T = 10 us     0x0008 - DQ3 is high DQ6 is toggling. DQ 5 and 7 are low. It should be erasing, correct?

@ T = 20 us     0x004C

@ T = 99 us     0x0108

@T = 15 ms    0x0000 - I was expecting the erase to take 500 ms, but looks like it completed and it is reading address 0x0 and it is not 0

@T = 30 ms to 500 ms   0x0000 same as above.

Would it be helpful for me to add more reads from 100us to 15 ms? How fast can an erase complete?

Randomly reading addresses some are 0x0 and some are 0xFFFF. Most are 0x0. 

I am thinking about erasing all sectors then reading random addresses again. 

Also note that when I read the Device ID I do get 0x227E. It is possible an address or data line could be wired wrong but we have checked it many times and since the Device ID and status registers seem ok, we believe the address and data lines are ok.