Nor Flash Forum Discussions

Hello Team,

Issue:  Reset pulse width of 1 microsecond is not working for new integrated flash (S29GL064S).

I have two flashes as below,

1. S29GL064N : In this flash we have use pulse width of 1 microsecond to reset flash and it works well, i.e., Flash gets restarted correctly.

2. S29GL064S : In this flash, we have same pulse width of 1 microsecond to reset flash, but here it does not work, i.e., Flash does not get restarted (it stucks). For testing purposes, we have provided 100 microseconds of pulse width and it works there.

Now my questions are:

1. What should be the exact pulse width to reset Flash and let Flash ready to start the system for both the Flash above.

2. Is there any difference between reset functionality for above mentioned flash? If yes, then please mentioned.

Please check and advise temperature reflow range for below part.

Infineon MPN:    S29JL064J55BHI000

Please send me the link to the document to download. 

Thanks.

1) how to program multiple memory locations 0x0000 0000 --->0x0000 0001 --->0x0000 0002..... in one transaction in SDR QSPI  .4S-4S-4S

2)then read in continuous manner with the help of mode with multiple  memory locations QSPI SDR 4S-4S-4S 

1.I'am reading the device id in 1s-1s-1s mode
2.enable 3 byte to 4byte by B7 cmd
4. reading all the registers values (status register 1-00h, status register 2-00h,cfgr register 1-00h,cfgr register 2-88h,cgfr register 3-00h,cfgr register 4- 08h) by 65 cmd with respective addresses(32 bits-1f in hexadecimal ) with read cycle of 8 bits .
5.enable write to volatile registers (cmd 50)
6.write enable cmd 71 with address and data , first iam writing in cfgr 1 -data 02 bit[ 1] should be high to enable 1-4-4 mode
7.write to volatile register 50 cmd
8.write enable cmd 71 with address and data , then iam writing in cfgr 2 -data E8 bit[ 6] and bit [5] should be high to enable 4-4-4 mode, this I'am writing in 1-4-4 format then its is convert to 4-4-4
9. after writing into all the registers i'am reading cfgr 1 ans cfgr 2 the values it showing is for cfgr 1-22 and for cfgr 2-33 that all are wrong values can you tell what is the issue i checked value for status register's also after write immediately it showed the value 02 means write is happening but i'am not getting where the issue is , that registes read and write in diff diff mode i have done that properly and also checked thrice?
see the attached pdf  quer 2

can you help me with setting the latency cycles of memory read?

Frequency 100MHz

 QSPI 4s-4s-4s SDR 

I had set the CFGR2V to C2

Read command :- 0C to read memory data

• Read command : 0C --> ADDRESS : 0x00000020 ---> MODE: 0x0000000A --->read cycles 32 bit 

Iam trying to read the memory data. I'm getting 85A5 A5A5A. Actual data is A5A5 A5A5 . 

the image attached is of reading the quad spi data of data line 2 and 3 because 1s-1s-1s is working proper with frequency 100 Mhz  in that we can observe its missing few cycles .

can you pls suggest what is the cause ?

I am able to communicate with the same family device with larger density (S26KL256)which is  and able to read the its ID using ID (Autoselect) Entry command I used same sequence to read the IID of S26KL128 Nor flash but I am getting all FFFFF. I think the device is not turning on properly for S26KL128 but it works for S26KL256. Even though both are of same family the S26KL128 is not responding. Do I have to turn ON that device differently I used same code to read IId from the device do I have to power on the device differently do we have to ramp up the voltage instead of directly setting it to 3.3V?

Hi ,

I'm using the flash chips of Cypress  S25FL256SAGBHI300 , and the WIP bit in the Status_register_1 indicates always a 1 and never 0 even after a power ON/OFF/ON .

Is it possible to clear that bit ?

Thanks for your help.

Alex