Nor Flash Forum Discussions

Dear Team,

We are using S29AL008J55TFIR10 NOR Flash in one of our board design.

we have to do the thermal analysis of PCB Board. so for this we required thermal parameter of all parts used in this design.

We did not found thermal parameter (RθJA, RθJC, RθJB) info of S29AL008J55TFIR10 this part in the respective datasheet.

so requesting the community to provide this parameters.

RθJA,

RθJC

RθJB

Thanks & regards,

Divya

I can see FL-S and FL-L have internal pull-up registor from Signal List of these datasheets.

What is the register value for the internal pull–up registor at below pins?

#1.RESET#

#2.WP#/IO2

#3.HOLD#/IO3

Part#

1).S25FS064SAGMFB010

2).S25FL128SAGMFMG00

Thank you

Would you please tell me what the meaning of the last "A"?

I suppose this is not marked by Cypress since there is no explanation on datasheet.

Thank you，

Shun Furusawa

Hi Team,

Please let me know the difference between  S29PL127J60TDI130H and S29PL127J60TFI130.

Thanks and regards,

I think this is my first post so hello everyone!

I would like to know if one of the S25FL NOR memory series, the S25FL256, would be a suitable configuration memory for an Arria 10 FPGA in an Active Serial configuration scheme (i.e. the FPGA actively reads data from the memory using a 1-bit serial interface). The FPGA model I am working with requires at least a 256-MBit configuration memory with a 1.8V interface, so I am considering to add a S25FL256 to my design setting the IO supply voltage to 1.8V. I have taken a look at this application note (AN98540) and I figured out the required circuitry, but I noticed the Arria 10 family is not included in the AN. Also I have noticed that the "official" serial memories that Altera manufactures and endorses for Arria 10 FPGAs (the EPCQ-L devices) are not functionally equivalent to the S25FL NOR memory series, so...

Does anyone know if a S25FL memory with enough capacity and proper interfacing would be suitable to configure an Arria 10 in active serial mode? I mean, will the FPGA be able to automatically read data at power up from this memory and load a configuration file?

Thank you very much for your time in advance and best regards,

P.

Hi,

I try to replace EPCS16 by S25FL128SAGMFI011,

I follow  the steps in "AN98558 In-System Programming for Cypress SPI Flash on Altera® FPGA Board" to program the flash,

that every thing look fine in Nios II command shell, but actually my program is not working......

I check my  FPGA  CONFIG_DONE pin and nSTATUS pin,  both are HIGH after the command "nios2-flash-programmer --epcs --base=0x120400 <myr design file>.flash", then I reboot my FPGA, both these pins become LOW.

Is this mean the problem is my FPGA configuration failure??

My FPGA device is Stratix II EP2S15F672I4N, and Quartus II version is 13.0 sp1.

(Besides, I have also tried to program .jic file by "Disable EPCS ID Check" in Quartus II 13.0 but not working)

Here is my Qsys setting:

Any suggestions? I need help.......

Thanks!

Hello,        

I use NOR flash memory from the Cypress family s25FL127s.

Could you please give me access to the source code for "Spansion FFS" ?

THANK YOU!

Hello,

There is a question about the description of the Data Sheet P39 "Table 5.3 Data Polling Status".

The output of DQ2, DQ6 has states of No-Toggle and N/A.

What exactly will each output look like?

Example)

· Do not toggle and keep the value at the time of last stop

· Do not toggle and output "0"

· Unspecified (1 or 0)

Best Regards,

Naoaki Morimoto

Hi, I am using S29GL256S10T flash in my design but these devices have a 16-bit (word) wide data bus and use only word boundary addresses. I need alternate part with same footprint and same pin mapping which support Byte wise boundary addresses or both byte wise and word boundary addresses.  same foot print and same pin mapping please provide me the solution