Nor Flash Forum Discussions
We have a PicoZed board with the S25FS128S QSPI that uses Xilinx FSBL, u-boot, etc. and everything worked perfectly until we had some event that cause the OTP bits in the configuration register to be set. By default, the FSBL uses the Zynq QSPI controller interface to read from the S25FS128S. However, the S25FS128S is in some sort of state that causes the linear read (memcpy from mapped addressed) from the QSPI to skip the first 32-bit word and thus fail to boot. I modified the FSBL to use the S25FS128S Quad Read command directly and that works fine (does not skip the first word). Any idea what state the S25FS128S chip is in that would cause the Zynq QSPI controller to not function correctly?
Thanks!
Show Lesshello,
I have trouble understanding the idea of base address and offset in NOR flash? If you can help me understand the idea behind bank, base address and offset that will be great. I am trying to read and write on flash based on ARM processor and mbed. If you can provide me an example code in c or c++ to read and write on the nor-flash I would more than appreciate it?
I am more of myself from software background and recently started developing embedded project.
Show Lesshello, my team and I are working on project where by we want to be able to store and pull up data from a S29GL512S memory, we struggling on getting a reference design or lay out guide lines since data sheet does not provide enough on how to do so. we running 32bit MCU. I will appreciate some help or suggestions.
Show LessDear Cypress,
I need a verilog model of S25FL064L.
Have you already prepared the model?
(FYI) I searched the following site, but I could not find it.
http://www.cypress.com/products/64mb-256mb-fl-l-nor-flash-memory
Best Regards
Show Less
FPGA cannot be configured although VIVADO says the bin file has been successfully downloaded into the SPI FLASH(S25FL128SAGBHIA00). I'm not sure if there's something wrong in the schematic. Can someone take a look at my schematic?
Besides, the power of Bank14 is 2.5V. FLASH_CCLK is connected to CCLK_0 pin (E8) in BANK0.And the FPGA chip is XC7A15T-1FTG256C.
Any advice is appreciated. Thank you in advance.
Show LessHello,
could s.o. please tell me the FIT value and its reference conditions / confidence level of the Flash Memory S25FL256S.
Thank you in advance.
Robin
Show LessI try to read some bytes in QPI mode and I read always the same byte 0xCC.
Operation is: first after power up, enter QPI Mode command, then PP (02h) page program in QPI mode and Quad I/ORead in QPI mode.
Address length is 24 bytes, clock frequency 10MHz.
Any suggestion? Maybe must be some previous initialisation commands or configuration registers writing?
Javier
Show LessPlease let me know the weight of S25FL064LABMFI000.
490mg?