Nor Flash Forum Discussions
I am not having any success in writing the volatile configuration registers in the S25FS256T samples (S25FS256TDACHC113) Infineon sent me using the commands WRENV_0_0 (Write Enable Volatile) and then WRARG_C_1 (Write Any Register). The old write enable command, WRENB_0_0 preceding the WRARG_C_1 command does work on the actual device in the lab. The Verilog model supports both WRENV_0_0 and WRENB_0_0 write enable commands when followed by the WRARG_C_1 command. Has anyone seen this problem on an actual S25FS256T flash?
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I'm using S25FS512SDSMFI011 to load boot code in my LS1046A project.
Do you have one patch to disable 4K Parameter Sector in uboot for me to refer to.
I want to use Uniform Sector Architecture, I know I need to change CR3NV[3] to 1 from default 0. But I don't know how to write code in uboot. My uboot is U-boot 2021.04 version. Any code is help for me to refer to. Thanks.
Show LessHi,
I would like to know the max operating junction temperature for S25FL512SAGMFI011.
Thanks!
What kind the command should I use the write the Code to S29GL128S10DHIV20 ?
Regards
Tom
Dear Team,
Kindly advise on below query.
We are using a S32K314 NXP microcontroller, but NXP says that it does not have dual chip select in the MCU's hardware, so we cannot use this Infineon QSPI with this controller (Not able to access full storage 1Gb).
With S70FL01GSAGMFM013, we are only able to access 512Mb of single sector storage, which is insufficient for our application. Whether it will support or not.
Show LessI confirmed the timing with datasheet.
I confirmed a timing in the datasheet.
But,I could not find that timing more than once sector-write(WE#) control.
Can It stay LOW CE#-pin during more than once sector-write(WE#) control?
And tWPH was 30ns(as speed-70) in the datasheet.
If It can stay LOW CE#-pin during more than once sector-write(WE#) control.
How long can I space each "tWPH"s?
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(1) In datasheet P51, ICC1 is the current consumption when reading from FPGA, etc., and ISB1 is the current consumption when chip select is high and flash is disabled after reading,
ISB1 is the current consumption when chip select is set to "H" and flash is disabled after read, is this correct?
(2) Regarding the internal resistance value
Can you tell me the internal resistance of the input/output pins of S25FL064P0XMFA003?
Translated with DeepL
Hello,
Have Data retention and cycling endurance test been made for this type of memory?
Is there a formula for calculating the lifespan of the memory depending on the cycles?
Thank you in advance!
Hi.
My customer is considering "S29JL064J70TFI000".
There was a description like the figure below in the guide that was in the spansion era.
Should I still be concerned about this phenomenon?
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(6) Precautions when using toggle bit
Toggling is normally done by DQ6 alternately outputting “H” and “L” at each /OE access.
When using /CE and disabling /OE access, the following precautions are required.
I will.
When using the toggle bit for termination detection, increasing /CE
If you try to disable /OE access, /CE comes up and then /OE comes up.
It is necessary to take 5ns or more before it falls.
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best regards
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Hello, I have two chips to find replacements, please help to find the model of Infineon. [MT25QL128ABA8ESF-0AAT][MT47H64M16NF-25E AAT:M]Micron.
No need to change the original PCB and software。
Thank you.
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