Nor Flash Forum Discussions
Hi everyone. I am working with the S29GL01GP device. When I try to program the memory, I see that the RY/BY pin goes high before the estipulated time of 60us (tWHWH1). I am measuring around 7 us.
I also figured out that when this happens, the data is not programmed. Is this some kind of warning of "write not successful"?
Thanks for your help.Show Less
Can anyone provide me parallel NOR flash driver for S29GL-S.
Please provide me polling syntax in case of sector Erase and word writing for same PART number.
Raj kishorShow Less
I am trying to understand what will happen to a NOR flash after a single sector is erased to the maximum capacity:
1.- How do you expect this sector will behave (in terms of malfunctioning) when writing and reading?
2.- Will this defective sector have any influence in the other sectors that have not been used?Show Less
We use a S29AL008J70TFI03 part and now find that the 03 (top boot sector, no CFI support) is not available. I am looking for recommendations for an alternate. Thanks in advance.Show Less
Hi, I am struggling to show that the timing analysis for the S25FL256S SPI Flash memory holds for Figure 5.10 SPI Single Bit Output Timing of the Document Number: 001-98283 Rev. *J.
The issue is that the Clock Low to Output Valid (tV) parameter max time delay is 8 ns, which violates the read operation setup time for AM3358 processor running in master mode with 48MHz clock frequency and 45/55 clock duty cycle. The AM3358 processor' Setup time(tsu(SOMI-SPICLKH)) (SOMI) valid before SPI_CLK active edge is 3.02 ns. Setup time margin = half period x duty cycle - tV - tsu = 9.36 - 8 - 3.02 = -1.66ns. However this example is application specific and out of your control, but I wanted to add the calculations for clarification.
Now assuming that one would like to run the SPI memory at say 100 MHz = 10 ns period = 5 ns half period, then given the Clock Low to Output Valid (tV) parameter max time delay of 8 ns and ignoring the delays related to clock duty cycle and master setup delays this should theoretically not work.
Please advise what am I missing..Show Less
Does anyone know the specifics of the "Z" model number. I do not see that one listed in the datasheet under ordering information. Can you please tell me the latency type, package details, reset# and VIO support.
We recently switched a board from the S25FL512S to the S25FL256S / 256kbit sector option, and have noticed that after a Bulk Erase or 4SE command, the flash will respond to a RDSR1 command with all bits set the first time, and then subsequent reads of RDSR1 will correctly show the WIP bit and write success, error bits will be 0 etc. We never saw this on the S25FL512S, code is basically the same.
Inserting a few (2-3) dummy reads of RDSR1 seems to be working as a work around, we're able to poll WIP after the first dummy read.
Is it normal to sometimes read the status register as all bits set / will the flash not drive the status register bits sometimes (we do have 1k pullups on MISO)? Is there a minimum wait time between bulk erase and polling RDSR1? SPI frequency is 2.5MHz, both mode 0 and mode 3 act the same. Flash is factory default settings afaik.
My manager is unhappy with the long lead time on S29GL512T10TFI010 . Is there a similar alternate that is form-fit (layout) identical to this device? Thank you.
Troy 🙂Show Less