Nor Flash Forum Discussions
Hello,
I have a custom board that uses S29GL01GS Parallel NOR flash (128 MB) connected to imx6q processor through EIM bus.
While booting I get the following error :
of-flash 8000000.nor: do_map_probe() failed
My linux kernel is 3.14.1.1.
This is my device tree configuration:
&weim {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor_2 &pinctrl_weim_cs0_2>;
#address-cells = <2>;//see below:1 cell for 4 hex digits
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
status = "okay";
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x04000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x10610281 0x00000001 0x0b020000
0x00008000 0x1c000000 0x00000000>;
};
};
Is there any patch to support this NOR flash?
Thanks and regards,
Sumish
Show LessCan anyone provide a recommendation for replacement of an obsolete chip, the M29W320EB?
Also, what usually dictates what flash can be used? I am developing a board with an ADSP-21489 processor if that helps. I see no specification in their documents about choosing flash other than the fact that they used the M29W320EB, and was told to contact a flash vendor for a recommendation when I asked about it.
Thanks,
Trevor
Show LessIf the part is placed in QSPI mode, is it still capable of receiving legacy serial commands even though it's set to QSPI?
Reason: I would like to have 2 masters access the flash. One master communicates vias QSPI and the second master via serial. The signals would be muxed. The QSPI master is default but in case of failures, the serial master would mux the signals, disconnect the qspi master, and reprogram the golden image.
Thanks
Show LessHello,
I hope this question still finds the right people, for there was no place for memory in general.
I am currently writing my bachelor thesis about the evaluation of filesystems for flash memory.
There is two options: Either using a NAND flash with ECC, or using a NOR flash without.
Because I didn't find any filesystem that applies Error Correction on NOR flash devices.
So the question is what Bit Error Rates I am going to get from a raw NOR flash and from a raw NAND flash device.
I didn't find any data on the internet and the documentation section of cypress, so I am asking, if any one of the community could provide me with such data.
Thanks in advance!
Show LessDear sirs,
About Whisker for S29GL064S
Please advise us if this document on HP will be available for PNOR Flash Memory,or not.
http://www.cypress.com/file/118321/download issued 2012
Regards,
Show LessHi, Can some one recommend replacement for S29PL032J,S29PL127J series parts?
As per PTN181204 issued, there is no replacement provided. For new designs the only option we could go with is GL-S, GL-T series? Please confirm.
Show LessHi
I am using the flash chips of CYPRESS, but I have a question that i don't understand..
At the Sector Erase part, after the erase command is sent to the chip, the internal erase cycle will be initiated, and the WIP bit will indicate a 0 when the erase cycle has been completed.
But where could I know the how long is the erase cycle? or how long the sector erase command takes to complete the sector erase step(after the CS# is set to high)?
And for the Bulk erses commond, the erset cycle is the same time?
Thanks .
Show LessHi,
Can we use S70GL02GS11FHI020 as a drop-in replacement for the S70GL02GS11FHI010?
The only difference I see is xxxx10 has highest address sector is protected and xxxx20 has lowest one protected. If we are not protecting any sector for our application then do we need to worry about using either one?
Also if we are looking to use S70GL02GT11FHI010, which has same characteristics as the GS part based on the data sheet except the GS part is dual die package and GT is not.
Does this matter to the u-boot and Linux driver?
Appreciate your response.
Thanks.
Regards,
Raj.
Show LessHi
At the datasheet of S25FL128SAGNFI000, Part 9.3.7 Write Registers (WRR 01h),it says
"After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the
Status Register to enable any write operations."
When WREN 06h was sent to the flash chip, and the CS goes high, then the WEL should be set enable.
There is the question, how long it takes between the CS goes high and the WEL gets enable?
Sorry to ask that , i can't find it in the datasheet...
Thanks ...
Show Less