Hello,According to specification,"When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to a...
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Hello,
According to specification,
"When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow 1
cycle of additional time for the host to stop driving before the memory starts driving the 4-cycle DLP."
The following is the description of DDR latency cycle from specification:
"
During the latency cycles, the host keeps CS# low. The host may not drive the IO signals during these cycles. So that
there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between host
and memory when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern
(DLP) during the last four latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so
that there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP. When
there are more than four cycles of latency the memory does not drive the IO signals until the last four cycles of latency."
The question is what is the expected behavior when DDR QUAD Read (EDh, EEh) is issued while DLP is enabled and the configured latency cycles are fewer than five cycles.
Option A: The DDR QUAD Read command is ignored.
Option B: The command is executed but without DLP (as if DLP is disabled). The set latency cycles are preserved and following them data is output on IO signals. If latency cycles are zero, then data will be output directly after address.
Option C: The command is executed but without effective latency cycles. DLP in initiated directly after address. If latency cycles are four, then full DLP pattern is output. If latency is less than 4, partial DLP (partial data preamble) is output on I/O signals before data.
Option 😧 This is a hybrid option of option B and option C listed above. If latency is 4, DLP is initiated. If latency is less than 4, DLP is not initiated but latency will be fulfilled as dummy cycles preceding data . Following those cycles, data is output on I/O signals.
Option E: Assume that the default value for latency is 5 when DLP is enabled. So even if it is configured to a value less than 5, 5 cycles will be considered.
Thanks,
Mona
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