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Hi, can anyone help me with the spi flash verilog simulation model?

I'm using verilog behaviorial model downloaded from https://www.cypress.com/verilog/s25fl256s-verilog .

I'm having trouble understanding some code when I'm doing the simulation with my own flash controller written by Verilog.

In "s25fl256s.v" from line 3107to line 3166, as we can see below, it defines erase time(seo),erase suspend time consume(elaspsed_ers) and erase resume(which restart the erase process).From line 3142, we can see that everytime entering erase suspend, it disable the edone_process(erase done time count) and set "duration_ers = seo - elapsed_ers", from my understanding, shouldn't it be "duration_ers = duration_ers - elapsed_ers"? Because everytime entering erase suspend, duration should decline and everytime we resume erase, the duration should count from what we've suspended, but not from the start "seo".

I'm not sure if I'm getting erase suspend and resume right..?

I've already sent email to the support email  the simulation model suggested, but haven't got replies yet. Hence I ask my question here.

Hope for your reply. Thanks a lot!

Dear all.

Now I am using the cypress SPI flash memory : S70FL01GSAGBHIC10.

And I need to see current CR register configuration status especially SPI QUAD bit.

Our questions are as the following and if you have some tips or ideas for them, please give me your recommendation.

Thank you.

1. I want to see current configured bit-values in CR register in memory dump information read by ROM Writer except for the use
   of RDCR instruction. Is it possible to see it ?
2. What address of CR registor is in memory?
3. CR registor is located in Sector Area of this memory?
4. Is there any tools released from cypress to see the configured bits in CR registor ?

Best regards,

WonjinHan.

Hi There,

I notice the WIP always busy non stop. May I know what happened?

here is my code

#define CMD_S25FLXX_WRITE_ENABLE      0x06  /* write Enable */

#define CMD_S25FLXX_READ_STATUS_REG   0x05  /* read Status Register */

#define CMD_S25FLXX_PAGE_PROGRAM      0x02  /* Page Program */

#define ADDRESS_1 12304

static uint8_t buf_data[34] = {0};

int main()

{

     uint8_t test_data[7] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07};

S25FLXX_write_data(ADDRESS_1 ,test_data,7);

S25FLXX_wait_ready();

}

/* CHECK CHIP READY*/

void S25FLXX_wait_ready(void)

{

do

{

        nrf_delay_ms(10);

buf_cmd[0] = CMD_S25FLXX_READ_STATUS_REG;

/* reset transfer done flag */

spi_xfer_done = false;

APP_ERROR_CHECK(nrf_drv_spi_transfer(&S25FLXX, buf_cmd, 1, buf_data, 2));

S25FLXX_spi_wait_until_transfer_is_completed();

                printf("buf_data:%d\r\n",buf_data[1]);

}

while ((buf_data[1] & S25FLXX_BUSY) == S25FLXX_BUSY);

}

/* WRITE FUNCTION */

uint8_t S25FLXX_write_data(uint32_t address, uint8_t* buf, uint16_t length)

{

if (! S25FLXX_is_busy())

{

uint16_t i;

uint16_t len;

uint8_t offset;

/* Write Enable */

buf_cmd[0] = CMD_S25FLXX_WRITE_ENABLE;

/* reset transfer done flag */

spi_xfer_done = false;

APP_ERROR_CHECK(nrf_drv_spi_transfer(&S25FLXX, buf_cmd, 1, buf_data, 1));

S25FLXX_spi_wait_until_transfer_is_completed();

/* Page Program */

buf_cmd[0] = CMD_S25FLXX_PAGE_PROGRAM;

buf_cmd[1] = (uint8_t)((address & 0x00FF0000) >> 16);

buf_cmd[2] = (uint8_t)((address & 0x0000FF00) >> 8);

offset = (uint8_t)(address & 0x000000FF);

len = ((S25FLXX_PAGE_SIZE - offset) < length) ? (S25FLXX_PAGE_SIZE - offset) : length;

// len = length;

buf_cmd[3] = offset;

len += 4;

for (i = 4; (i < len); i++)

{

buf_cmd = buf[i-4];

}

/* reset transfer done flag */

spi_xfer_done = false;

APP_ERROR_CHECK(nrf_drv_spi_transfer(&S25FLXX, buf_cmd, len, buf_data, 1));

S25FLXX_spi_wait_until_transfer_is_completed();

return S25FLXX_OK;

}

else

{

return S25FLXX_BUSY;

}

}

we using the Flexspi to access s25fs128s model and using read command 0x3. but the model i/o signal without timing information even I load the SDF file _verilog.sdf. the file is download from cypress website. currently, The model (s25fl128s.v) is add in my top testbench and using S25FS128SAGMFI100_F_30pF in the Timings25fl128sModel. and using the $sdf_annotate task to load the SDF file. From s25fl128s document I 3.3.2 I using method 1 to generate SDF file because method 2 is for VHDL. so I don't know which step is missing in my simulation.

the waveform is shown below and this is a model i/o signal. currently, we can't get the correct value from SO. and always get z. so how to let  s25fs128s i/o have timing information?

Thanks

Could you provide S-parameter of below part#.

Part#: S25FS512SAGMFB01x

Thank you & Regards,