Nor Flash Forum Discussions
Hi,
I am using SPI Serial Flash Memory, 512Mbit, SO16 package in one of my design. I am finding many chips getting faulty in 5 to 6 months of operation in field as all access fail post that.
On analyzing one of the field return card. I am able to read device ID of this part but starting few sectors read/ write is not consistent and finding number of places data read not matching with data written.
We tried to reprogram multiple times but data integrity is not there in various sectors belong to first bank.
Device ID is getting detected by firmware always. Just printing one uboot print of processor log.
Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB
Since data is not consistent in various sectors and we are using this as processor boot memory, so processor gets stuck during bootup.
We are using mostly first bank (16MB) location only for processor uboot. On faulty chip, we found read/write access to locations 4MB onwards (all 3 banks except first) is ok. Since it is processor boot memory, so would be read just once during processor boot and write only if any image upgrade needed which is rare.
Datasheet mentions 100,000 Program-Erase Cycles on any sector typical. These sites are not having power backup and almost gets power cycle on daily basis but it does not explain endurance of sectors.
We noticed that part S25FL512SAGMFIR11 used is with VIO option but this pin is kept NC in our design. Measured voltage at this pin is 3.3V but dips to 2.5V while doing any access in working chips too. Below is the measurement done in one of the working board.
Host is operating at 3.3V IO level which is the same supply of flash VCC.
Thanks
Anurag
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The S29AL008J70BFI010 datasheet lists the sector trace time as "10s",
The S29AL008J70BFI010 datasheet lists a maximum sector trace time of 10s.
I understand from the above description that if it takes more than 10 seconds to execute a sector trace, it is considered to be abnormal, Is this correct?
Please tell me about θjc or Ψjt and θjb or Ψjb of Infineon S29AL016J70TFI010.
S25FL128SAGMFI000
Do you have experience with the above model numbers operating at clock frequencies below 300 kHz?
Hello,
I am using S25FS512SAGNFI011 Nor Flash for the FPGA Arria 10 configuration. I generated .jic file from .sof file as described in the document AN229767 of Infineon. I get the successful result on the tool when I load the file to the flash, but the FPGA does not boot up after power cycle.
My settings for the generating the file are below:
I'll be glad if you can help me.
Best regards!
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While attempting to flash data onto the memory, we have encountered persistent problems with memory corruption and functionality. Specifically, we have observed that errors are consistently popping up within the address range of 0x00000000 to 0x00002800.
Also, while erasing memory errors are popping up in given images
We've tried troubleshooting but need urgent assistance to resolve this issue.
Thanks & Regards
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S29PL032J70BFI120 and S29PL032J70BFI070
What is the difference between these two products?
Are there any differences between them?
1) specification
(2) usage
(3) materials
(4) process
(5) production site (6) others
⑥others
Hi folks,
We use a S29GL01GT12DHVV10 for FPGA configuration memory. I am currently working on stress analysis and couldn't find any information in the datasheet for current of VIO pins. I believe all the max current consumption values on sheet 3 are for VCC. Looking for both a worst case/max and typical draw.
Thanks,
Allen
Show LessPSCK/tCH/tCL are available as AC specifications for SCK duty ratio, and for tCH/tCL, Notes 30,
Notes 30. ±10% duty cycle is supported for frequencies ≦ 50MHz.
(Confirm AC specs regarding SCK duty ratio: tCH/tCL)
When using SCK frequency: 333 kHz (PSCK: 3000 ns [cycle]), which of the following AC specification values for tCH/tCL is supported by Note 30?
Which of the following is the AC spec value?
When FSCK > 50MHz, the value is 45% (=50%-5%)xPSCK.
tCH(Min) = (50%-10%)xPSCK : (40%)1200ns
tCL(Min) = (50%-10%)xPSCK : (40%)1200ns
Or does it mean that up to ±10% duty cycle is possible?
tCH(Min) = 10%xPSCK : (10%)300ns
tCL(Min) = 10%xPSCK : (10%)300ns
Hi,
Please let me know processing across the boundary between Die1 and Die2 of S25HL02GT,
For example, when program 32 bytes from 07FFFFF0h, is one transaction acceptable?
Or do I have to split it into two transactions?
Best Regards,
Kumada
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