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Shraddha
Level 3
Level 3
First solution authored 50 sign-ins 10 questions asked

Iam giving the configuration correct as you mentioned 

read command for status registers  65h

write into volatile register cmd 50 after that 71h address data type 

for reading device id AF mode 

 you can refer the memory window  

 

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Shraddha,

    < 2nd Notice >

Thank you for contacting Infineon Technologies.

Configuration Register-1, bit-1 (CFR1N[1]) and Configuration Register-2, bit-6 (CFR2N[6]) must both be set to configure the S25HL512T into the QUAD mode, hence:

CFR1N[1] = QUADIT = Quad SPI Interface Selection - I/O width set to 4 bits

 Selection Options (either '1' or '0'):
  0 = Data Width set to 1 or 2 bits wide (1x - Single, 2x - Dual)
  1 = Data Width set to 4 wide (4x - Quad) 

CFR2N[6] = QPI-IT = QPI Interface & Protocol Selection - I/O width set to 4 bits (4-4-4)

 Selection Options (either '1' or '0'):
  0 = Data Width set to 1 or 2 bits wide (1x - Single, 2x - Dual) - Legacy Protocol
  1 = Data Width set to 4 wide (4x - Quad) - QPI Protocol

With regards to the Quad Transaction names for 1S-4S-4S or 4S-4S-4S, use transaction name " RDQID_0_0 ".

What are the current register settings for CFR1 and CFR2?

 

Best regards,

Albert

Cypress Semiconductor Corp.

Infineon Technologies Company.

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Shraddha,

Thank you for contacting Infineon Technologies.

Configuration Register-1, bit-1 (CFR1N[1]) and Configuration Register-2, bit-6 (CFR2N[6]) must both be set to configure the S25HL512T into the QUAD mode, hence:

CFR1N[1] = QUADIT = Quad SPI Interface Selection - I/O width set to 4 bits

 Selection Options (either '1' or '0'):
  0 = Data Width set to 1 or 2 bits wide (1x - Single, 2x - Dual)
  1 = Data Width set to 4 wide (4x - Quad) 

CFR2N[6] = QPI-IT = QPI Interface & Protocol Selection - I/O width set to 4 bits (4-4-4)

 Selection Options (either '1' or '0'):
  0 = Data Width set to 1 or 2 bits wide (1x - Single, 2x - Dual) - Legacy Protocol
  1 = Data Width set to 4 wide (4x - Quad) - QPI Protocol

With regards to the Quad Transaction names for 1S-4S-4S or 4S-4S-4S, use transaction name " RDQID_0_0 ".

What are the current register settings for CFR1 and CFR2?

 

Best regards,

Albert

Cypress Semiconductor Corp.

Infineon Technologies Company.

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AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Shraddha,

    < 2nd Notice >

Thank you for contacting Infineon Technologies.

Configuration Register-1, bit-1 (CFR1N[1]) and Configuration Register-2, bit-6 (CFR2N[6]) must both be set to configure the S25HL512T into the QUAD mode, hence:

CFR1N[1] = QUADIT = Quad SPI Interface Selection - I/O width set to 4 bits

 Selection Options (either '1' or '0'):
  0 = Data Width set to 1 or 2 bits wide (1x - Single, 2x - Dual)
  1 = Data Width set to 4 wide (4x - Quad) 

CFR2N[6] = QPI-IT = QPI Interface & Protocol Selection - I/O width set to 4 bits (4-4-4)

 Selection Options (either '1' or '0'):
  0 = Data Width set to 1 or 2 bits wide (1x - Single, 2x - Dual) - Legacy Protocol
  1 = Data Width set to 4 wide (4x - Quad) - QPI Protocol

With regards to the Quad Transaction names for 1S-4S-4S or 4S-4S-4S, use transaction name " RDQID_0_0 ".

What are the current register settings for CFR1 and CFR2?

 

Best regards,

Albert

Cypress Semiconductor Corp.

Infineon Technologies Company.

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Shraddha
Level 3
Level 3
First solution authored 50 sign-ins 10 questions asked

hey albert ,

its working fine thanks for you updates 

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