S70FL01GSAGBHIC10 for Zynq Configuration

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Anonymous
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Hi,

I'm planning to use the S70FL01GSAGBHIC10 QSPI for Zynq configuration.  Since this part is a dual stacked 512Mb chip, it contains two chip selects.  I can connect these two chip selects to the Zynq MIO pins 0/1.  Should I connect the data lines from MIO2-MIO5 to MIO10-MIO13 and also to the QSPI?  Also, there are two clocks provided from the Zynq to run two separate QSPI chips.  Should I OR the two clocks together to connect to the single clock input on the QSPI?  Lastly, do the chip select signals on the QSPI require pull-ups or are there internal pull-ups on these signals?

Thanks for any help.

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TakahiroK_16
Employee
Employee
100 replies posted 50 replies posted 25 solutions authored

Hello,

With the S70FL01GS, you can configure Zynq QSPI as the "Dual SS, 4-bit Stacked I/O" which described in the Xilinx's document (UG585). In this configuration, you should connect MIO0/1 to two chip selects, MIO2-MIO5(QSPI0 IO0-3), and MIO6(QSPI0 CLK). MIO9(QSPI1 CLK) and MIO10-MIO13 (QSPI1 IO0-3) are not used.  There is no internal pull-ups on the Chip Selects in the FL01GS so please place external pull-ups.

Best Regards,

Takahiro

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