cancel
Showing results for 
Search instead for 
Did you mean: 

Nor Flash

KW
New Contributor II

Datasheet Rev L, In Chapter 7.2.4 it was written :

"The 8th word will continue to be driven until the burst operation is aborted (CE# goes to VIH, a new address is latched in for a new burst operation, or a hardware reset)."

But in Figure 13. it shows that the A/DQ pins turn into unknow after RDY disable.

The two are not consistent so make me confused, could you help update it?

0 Likes
4 Replies
AlbertB_56
Employee

Hello,

Thank you for contacting Cypress Semiconductor.

Please allow us to investigate this  datasheet.  We will communicate any new information

to you as soon as it becomes available.

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

AlbertB_56
Employee

Hello KW,

The statement on page 22 is not illustrated in Figure 13.  Figure 13 is trying to illustrate the read timings parameters before “//” as shown in the green rectangle.  RDY is flash output signal indicating if the flash output data is ready for controller to read.  RDY itself does not have impact on data bus. 

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

0 Likes
KW
New Contributor II

Hi Albert,

   Thanks for the declaration, but I think the diagram after "//" will be an ambiguous part that confusing with the behaviors in page 22 which expect DB to keep before CE disable.

Thank you,

Keter

0 Likes
AlbertB_56
Employee

Hello Keter,

Yes, the Applications Team agrees that this may be ambiguous/confusing, but  rest assured, figure 13 does not coincide in any way with regards to the verbiage on page 22.

 

Best regards,
Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

 

 

0 Likes