S29VS status polling using read status command

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KW
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I am using the memory verilog model in S29VS-R_VERILOG.zip. When I polling Status[7] after issuing "Buffer to Flash" in Secure Silicon Region, the model always feedback SSR array value instead of Status after programing done (current_state back to "SecSi_ENTRY"). I want to know if this is the expected behavior or something wrong there.

 

Verilog pieces  (Line# 2434~2460)

SecSi_ENTRY:
begin
if (falling_edge_WRITE)

...
if (oe)  // No status read branch here 
begin
    if (SecAddr == SA_SecSi)
    begin
        READMEM(ReturnAddr(Addr,SecAddr),SecAddr,SS_T);
        Dout_zd = OutputD;
    end
    else
    begin
       READMEM(Addr,SecAddr,Mem_T);
       Dout_zd = OutputD;
    end
end
end

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1 Solution

Hello,

Please refer to your email for our response.

Thank you

Regards,

Bushra

View solution in original post

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10 Replies
BushraH_91
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750 replies posted 50 likes received 250 solutions authored

Hello.

Thank you for contacting Cypress Technical Support, an Infineon Technologies Company. Currently we are reviewing your issue and will get back to you as soon as we find the resolution.

Regards,

Bushra

KW
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Thank you for the reply, also the issue exists when CR_ENTRY, the model will feedback value of ConfReg0 when (STAT_ACT==1) which I expect Status value to polling the flash programming status.

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BushraH_91
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Hello,

Are you using S29VS256R?  Please confirm.

About the status polling, please make sure you issue Read Status Register command (70h) before reading status. The S29VS256R does not support DQ status polling.

And about,

- Reads can be performed in the Asynchronous or Synchronous mode.

Async or Sync mode is a bus protocol between host and device. You can read in sync mode regardless of ASO.

Thank you

Regards,

Bushra

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KW
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Sure, I am using S29VS256R and polling status from status register.

For the status polling, this is my programming sequences while SSR entry programming:

1. 88h to enter SecSi_ENTRY when current_state is IDLE_RST

2. 25h to do buffer write

3. 29h to execute BUFFER to FLASH programming, and the current_state goes from WB_LOADED to PGM

4. 70h to read status and get correct status reg value when current_state=PGM

5. 70h to read status and get WRONG status value when current_state go back to SecSi_ENTRY from PGM after programming done. Instead the model feedbacks the SSR value.☹️

item #5 is the fail case I encountered. 

 

By the way, could you provide the simple testbench to run golden cases of s29vs256r.v for reference?

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BushraH_91
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750 replies posted 50 likes received 250 solutions authored

Hello,

We are still working on your issue. Please bear with us.

Thank you

Regards,

Bushra

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Hello,

Thank you for waiting.

We are suggesting to initiate Option A and B (detailed directly below). This will give some idea whether the Status_READ is working at all:

  1. A) With Status Read
  2. Execute command 88h to enter SecSi_ENTRY (device is idle)
  3. Execute command 25h to initiate ‘Write-to-Buffer’
  4. Execute command 29h to execute program ‘BUFFER-to-FLASH’ (device state goes from ‘Write-to-Buffer’ to program ‘Buffer-to-flash’)
  5. Execute command 70h to initiate status_READ and get correct status value (during program ‘Buffer-to-FLASH’)
  6. One second delay with Status_READ (command 70h) to get the actual Status Bits [7:0]
  7. Execute command F0h to exit from SecSi mode
  8. Execute command 88h to enter SecSi_ENTRY
  9. SecSi Region Read
  10. B) Without Status Read
  11. Execute command 88h to enter SecSi_ENTRY (device is idle)
  12. Execute command 25h to initiate ‘Write-to-Buffer’
  13. Execute command 29h to execute program ‘BUFFER-to-FLASH’ (device state goes from ‘Write-to-Buffer’ to program ‘Buffer-to-flash’)
  14. Execute command 70h to initiate status_READ and get correct status value (during program ‘Buffer-to-FLASH’)
  15. One second delay
  16. Execute command F0h to exit from SecSi mode
  17. Execute command 88h to enter SecSi_ENTRY
  18. SecSi Region Read

Please provide us your results.

Thank you

Regards,

Bushra

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Hello,

Please refer to your email for our response.

Thank you

Regards,

Bushra

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KW
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Could I know which overlay entries can be read out in Synchronous mode? 

According to SPEC Rev L, I only see the description below:

Chap 8.5  Secure Silicon Region

- Reads can be performed in the Asynchronous or Synchronous mode.

so I assume only main memory array and Secure Silicon Region can be read in Synchronous

How ever in the behavior model, the task READ_BURST_DATA list 3 cases for burst read

1. MEM_T

2. SS_T

3. ID_CFI_T

did I miss something in spec that mention ID_CFI region also supports read in synchronous mode?

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BushraH_91
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750 replies posted 50 likes received 250 solutions authored

Hello 

Modeling group is still debugging your issue. Please bear with us.

Thank you

Regards,

Bushra

KW
Level 1
Level 1
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Hi Bushra,

   This is to ping the status of the issue solving progress. and I list the current issue we encountered

1. Could we get status via cmd 70h when current_state is at SecSi_ENTRY & CR_ENTRYSSR_LOCK_ENTRY

2. When trying to program SSR_LOCK_REG[0] from 0 -> 1 (ILLEGAL ACTION for OTP region), the model will overwrite Mem with WrBuffData[i] (s29vs256r.v Line #3165~3186) which is unexpected.

3. When trying to program SSR_LOCK_REG[0] from 1 -> 1 (ILLEGAL ACTION for OTP region), the model will overwrite Mem with -1 (s29vs256r.v Line #3143~3164) which is unexpected.

4. What is the meaning of signals TimingModel & tmp_char, with default value I get ascii value "d" of tmp_char which the model seems expect "0" or "1". should I revise the default value of TimingModel ?

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