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Nor Flash Forum Discussions

yuxi_3250341
Level 3
Level 3
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Hi there,

I'm currently doing simulation with my NOR-controller design and S29JL064J Verilog simulation model. I experienced a strange behavior of DQ7 when I do Sector Erase simulation. A description of what I did is as follows.

1, The S29JL064J Verilog model is downloaded from Cypress official website; it's info is listed below:

Version: V1.1

Author: S.Petrovic

Date: 13 Nov 29

2, My simulation flow is as follows:

(1) Program 256 bytes of random data to NOR, starting from address = 00_1000h, and let address + 1 after each 16-bit-word program is finished successfully;

(2) Read 256 bytes from NOR, starting from address = 00_1000h, and I can see that these data are consistent with the data I programmed in step (1).

(3) Issue the Sector Erase command sequence to NOR, the address to be erased is 00_0000h.

(4) Read DQ7-DQ0 and go through the polling process.

3, What I saw in my simulation is:

Program and read seemed OK, which indicates that my simulation environment, my testbench, should be OK;

However, the first polling immediately after Sector Erase just gives me DQ7 = 1, which seems somewhat weird or strange.

4, Upon careful re-reading of S29JL064J datasheet, page 34 says: "During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or ..., Data# Polling produces a 1on DQ7."

So, in my expectations, the first polling should give me DQ7=0, but the S29JL064J simulation model seems to behave otherwise. My simulation waveform is shown below, all these signals are S29JL064J's port signals:

pastedImage_1.png

I mark my operations in yellow rectangles:

In the first yellow block, the NOR flash is fed with Sector Erase command sequence;

In the second yellow block, as you can see now RY/BY# (the RY signal near the bottom of the waveform) is low, which indicates the NOR device is busy doing internal erase operations, but polling DQ7 gives me 1, which is UNEXPECTED behavior.

5. To debug this, I delved a little bit deeper into the S29JL064J Verilog model. After grabing the model's FSM state into waveform, I can see that, with the input of Sector Erase command sequence, the FSM state machine's current_state signal (near the bottom of the above waveform) went through the following states:

RESET --> Z001 --> PREL_SETBWB --> C8 --> C8_Z001 --> C8_PREL --> SERS, and then it just stays in SERS state.

In the above timing diagram, while the S29JL064J's internal state machine actually stays in SERS(7'd17), the second yellow block the polling of DQ7 gives 1. Meanwhile, a signal "Status[7]" in the model just changes from 0 to 1 (last signal in the above waveform), which I guess should be the "1" that DQ7 captures.

From my amateurish understanding of the Verilog model, and by guessing from the "SERS" acronym, now the S29JL064J should be doing Sector ERaSe, but polling DQ7 gives me 1.

6. So, my question is, is there a possibility that the S29JL064J Verilog model might be giving wrong poll result at DQ7-DQ0 during Sector Erase?

Or, is my NOR controller issuing wrong commands to the S29JL064J Verilog simulation model?

消息编辑者为:yuanlu xie

消息编辑者为:yuanlu xie

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1 Solution
AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi xieyl,

I would like to inform you that our behavioral models are timing accurate and need SDF to work correctly.

Best Regards,

Apurva

View solution in original post

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4 Replies
AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi yuanlu xie,

Thank you for contacting Cypress Semiconductor.

I would like to know whether you are running the simulations with SDF or not?

Best Regards,

Apurva

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Hi Apurva, thanks for replying.

I am doing the simulation WITHOUT sdf files.

I'm currently doing behavioral simulation; as is directed in the model's "\S29jl064j\Model_Manual_English.pdf" document:

The model file model.v ...... does not depend on other files and can be run as is in a behavioral Verilog simulation.

For a basic simulation no files beyond the files used for compilation are required.

So, I think running the sim with only the Verilog file should be fine.

Thx & Best Regards

xieyl

March 06, 2020

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AS_36
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi xieyl,

I would like to inform you that our behavioral models are timing accurate and need SDF to work correctly.

Best Regards,

Apurva

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Hi Apurva, I got it, thank you!

Best Regards

xieyl

March 11, 2020

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