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Nor Flash Forum Discussions

FBW_HW
Level 1
Level 1
First question asked Welcome!

The current design uses S29AL032D70TAI030, targeting S29GL064S70TFI030 for a new design.

 

Would like to understand the potential for Neutron signal event upsets (NSEU) at altitude in the new device compared to the legacy device. The process size changes from 200nm to 65nm. Aerospace application.

 

Would also like to know if this device family (both new and old parts) are multi-layer cell (MLC) or single-layer cell (SLC) NOR flash architectures as this factors into NSEU susceptibility.

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1 Solution

Hello,

Please see below

 

The current design uses S29AL032D70TAI030, targeting S29GL064S70TFI030 for a new design.

Would like to understand the potential for Neutron signal event upsets (NSEU) at altitude in the new device compared to the legacy device. The process size changes from 200nm to 65nm. Aerospace application.

Answer: The new device is protected by embedded EDAC, so no issue for your application. The EDAC is not self-scrubbing, so it does not support single byte write operations.

Would also like to know if this device family (both new and old parts) are multi-layer cell (MLC) or single-layer cell (SLC) NOR flash architectures as this factors into NSEU susceptibility.”

Answer: The old part is a floating gate SLC cell where the new part is 2bit per cell architecture. It is not a classical MLC architecture, but could be considered as such.

Thank you

Regards,

Bushra

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BushraH_91
Moderator
Moderator
Moderator
250 solutions authored First comment on blog 500 replies posted

Hello,

Thank you for contacting Cypress Technical Support, an Infineon Technologies Company. Currently we are reviewing the case and will get back to you as soon as we find the resolution.

Regards,

Bushra

0 Likes

Hello,

Please see below

 

The current design uses S29AL032D70TAI030, targeting S29GL064S70TFI030 for a new design.

Would like to understand the potential for Neutron signal event upsets (NSEU) at altitude in the new device compared to the legacy device. The process size changes from 200nm to 65nm. Aerospace application.

Answer: The new device is protected by embedded EDAC, so no issue for your application. The EDAC is not self-scrubbing, so it does not support single byte write operations.

Would also like to know if this device family (both new and old parts) are multi-layer cell (MLC) or single-layer cell (SLC) NOR flash architectures as this factors into NSEU susceptibility.”

Answer: The old part is a floating gate SLC cell where the new part is 2bit per cell architecture. It is not a classical MLC architecture, but could be considered as such.

Thank you

Regards,

Bushra

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