S25HS256T_configure

[akurowski121]

Dear Community,

I am having problem with configuring S25HS256T flash memory located at SemperFlashClick module into specified configuration. It is:

- Quad I/O,

- DDR,

- Dummy (due to fact that documentation and SFDP say that DDR in Quad I/O mode needs 7 or more dummy cycles),

- Disable HOLD?

I already configured memory into Quad I/O mode by reading data using 0x35 command (Status Register 2) and then modify this register by writing two data bytes 0x02 along with 0x01 command (Write Status). In documentation there is written that memory can communicate through DDR, but in SFDP there is no information how to configure it. I think it works automatically. At that moment, memory can communicate with IO_Fastread_A32 command 0xEC. I assume that if I want to use DDR I have to set dummy cycles, but I am having problem with understanding how to do that. I think instruction how to do that is located at 9-10 DWORDS in Status, Control and Configuration Register Map in SFDP. Read values:

9 DWORD: 0x71 0x65 0x04 0x97

10 DWORD: 0x71 0x65 0x03 0xD0

Volatile address offset (1 DWORD): 0x800000

Non-Volatile address offset (2 DWORD): 0x000000

Now I understand that I have to read data using 0x65 command and 0x71 command to write data. I thought that I have to send frame: 0x65, 0x80, 0x00, 0x00 to read data and 0x71, 0x80, 0x00, 0x00, (read data | 0x80), 0x01 (2 bits which begin at 7th bit). That attempt does not work. Can somebody help me with the correct way to do that?

Sincerely,

Andrzej

[BushraH_91]

Hello,

Thank you for contacting Cypress Technical Support, an Infineon Technologies Company. We have received your inquiry and currently reviewing the issue. We will get back to you as soon as we find the resolution.

Thank you

Regards,

Bushra

[akurowski121]

Hello,

For configuration of the dummy cycles, I think I was sending wrong address bytes. I collected some information and I think that send frame has to be: 0x65, 0x00, 0x00, 0x03 (configuration register 2 NV?), 0 or 8 dummy cycles and then memory should send back data. Similar to that: 0x71, 0x00, 0x00, 0x03, 0 or 8 dummy cycles, read byte from previous chunk of data | 0x1C (for 7 dummy cycles). Am I getting in the right direction?

Sincerely,

Andrzej

[AlbertB_56]

Hello ,

The 65h command is for the 4-4-4 'Read Any Register' transaction

The 71h command is for the 4-4-4 'Write Any Register' transaction

I believe your commands may now be correct, as compared to your previous (initial) post.

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company 

[AlbertB_56]

Hello,

To better understand your issue, please specify as to which mode you wish to configure the S25HS256T.

In 4-4-4 transaction table, the 35h command reads Configuration Register-1, but not Status Register-1.  To read Status Register-1, use  05h command.

From your original statement, you had already configured the FLASH in QUAD I/O mode.  Are you attempting to configure the FLASH in DDR QUAD I/O mode?  It is not quite clear to me as to how you configured the FLASH in QUAD I/O mode, using Status Register-2.

1S-4D-4D: One DQ signal used during command transfer at SDR, four DQ signals used during address and data transfer at DDR.

4S-4D-4D: Four DQ signals used during command transfer at SDR, four DQ signals used during address and data transfer at DDR.

For Read DDR Quad I/O (1-4-4) :

  - 3-byte addressing = use EDh command

  - 4-byte  addressing = use EEh command

For DDR protocol, Mode 3 is not supported.

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

[akurowski121]

Thanks for your response!

I wish to configure S25HS256T memory to use DDR QUAD I/O Read as you wrote before. Basic Flash Parameter Table of the SFDP 15th DWORD (22:20 bits = 0'b101) suggest that:

"QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h with two data bytes, where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes, where bit 1 of the second byte is zero."

Due to that, first I have to use 0x35 command to read this register and then modify it by logical sum with 0x02. At the end, I have to send 0x01 command with 2 data bytes, where the second byte is this modified value.

I should remind earlier that I do not have full documentation of the S25HS256T memory. I am still waiting for response from Semper Access Program. Every step is done by reading only SFDP register map.

"The 65h command is for the 4-4-4 'Read Any Register' transaction

The 71h command is for the 4-4-4 'Write Any Register' transaction"

I understand that those command are not available in Single SPI, am I right?

To sum up:

If I want to use DDR QUAD I/O mode, I have to configure:

• QE bit, which is read by sending 0x35 command and writing 0x01 command with two data bytes, where second one is logical sum of the read data with 0x02 (to use 1-4-4 or 1-1-4)
• Dummy cycles, which are read by sending frame: 0x65, 0x00, 0x00, 0x03, 0 or 8 dummy cycles. Similar to that configuring dummy cycles is done by sending frame: 0x71, 0x00, 0x00, 0x03, 0 or 8 dummy cycles and 1 data byte which is logical sum of the read data with 0x1C

Sincerely,

Andrzej

[AlbertB_56]

Hello Andrzej,

Thank you for your response.

Yes, you are correct commands 65h and 71h do not exist in SDR mode.

Please allow me to check on your Semper Access Program registration status.

Best regards,
Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

[akurowski121]

Hello Albert,

Something is bothering me.

"Yes, you are correct commands 65h and 71h do not exist in SDR mode."

I assume You meant that 0x65 and 0x71 do not work on Single SPI, not SDR mode.

Basic Flash Parameter Table 15th DWORD in the SFDP register map suggest that to configure flash memory into QuadSPI mode (8:4 bits equal 0'b01000), I have to send data: 0x65, 0x80, 0x00, 0x03, 0 or 8 dummy cycles and then configure it by: 0x71, 0x80, 0x00, 0x03, 0 or 8 dummy cycles and 1 data byte which is logical sum of read data and 0x40. How to do that when 0x65 and 0x71 commands are available only in 4-4-4 mode?

Sincerely,

Andrzej

[AlbertB_56]

Hello Andrzej,

Yes, my correction...commands 65h and 71h are not supported in SPI mode, rather than SDR mode.   

The Semper Access Program invitation has been sent to you, please click in "Join this group hub' to gain full access to Semper collateral.

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies  Company

[akurowski121 · Accepted solution]

Okay, now it works. To communicate with memory with DDR Quad I/O Fast read:

• QE bit must be set, You can do that by sending 0x35 command and writing 0x01 command with two data bytes, where second one is logical sum of the read data with 0x02 (to use 1-4-4 or 1-1-4). Another way is to send frame: 0x71, 0x80, 0x00, 0x02, logical sum of read data and 0x02
• Dummy cycles, which are read by sending frame: 0x65, 0x00, 0x00, 0x03. Similar to that configuring dummy cycles is done by sending frame: 0x71, 0x00, 0x00, 0x03 and 1 data byte which is logical sum of the read data with 0x0A (for 10 dummy cycles)
• 0x65 and 0x71 commands work also in Single SPI

Thank you for Your help 🙂

Sincerely,

Andrzej

[AlbertB_56]

Hello Andrzej,

Thank you for the update...this good to know.

Did you receive the Semper Access Program (SAP) invitation, and clicked on "Join this group hub"?

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

[akurowski121]

Hello Albert,

Yes, I did. Documentation of the S25HS256T helped me a lot 😄

Sincerely,

Andrzej

[AlbertB_56]

THIS IS A CORRECTION TO A PREVIOUS STATEMENT WITHIN THIS THREAD :

     ORIGINAL STATEMENT =  "Yes, you are correct commands 65h and 71h do not exist in SDR mode."

     CORRECTION =  "COMMANDS 65h AND 71h  ARE SUPPORTED IN SPI MODE."

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company