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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Hello,

We are facing a wierd issue with the S25HL512T device that we have. The device was working smoothly until one of our colleague power cycled it on boot and since then we believe the configuration got corrupted. 

We can write the configuration if we reset all the registers to zeros but cannot identify the device in QSPI mode. It does identify itself in QPI mode (1-4-4) but without the configured latency cycles or in SPI mode with the configured latency cycles. Also, we do not read 0x61 or 0x41 in STR1 register so the Safeboot process could not be followed.

We are writing the following values to the registers:

CFG1: 0x2

CFG2: 0xc8

CFG3: 0xd0
CFG4: 0x0

We read back:

CFG1: 0x2

CFG2: 0xd8

CFG3: 0xd2
CFG4: 0x0

STR1: 0x0

We don't know why the reserved pins are set even when we don't write to them. How do we recover this device to work in QSPI mode?

And what does it mean to read 0xff value from all the registers in QSPI mode?

We cannot provide any waveforms since it is not possible to access & probe the device.

Thank you

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1 Solution
Yuvraj
Moderator
Moderator
Moderator
First question asked 250 replies posted 25 likes received

Hi,

What you stating here is correct. This is what is expected,  You will not be able to read or operate in SPI or QSPI mode.


Once the device is set in 4-4-4 mode if you want to set it in SPI or QSPI mode you need to 
change CFR2N[6] / CFR2V[6].

To change these bits you have to use write commands as per 4-4-4 (QPI) mode.

Make sure you write the configuration register as per QPI commands.

Regards,

Yuvraj 

View solution in original post

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23 Replies
YukaA_81
Employee
Employee
5 solutions authored 10 replies posted First like given

Hi,

My understanding is that you want to use it in QSPI mode (1-4-4), is that right?

If so, the CFR2N[6] QPI-IT should be "0".
In your current configuration, it is set to "1", so you use QPI mode (4-4-4).

Also, what is the frequency?
You need to adjust the latency cycle according to the frequency you are using, so please set CFR2N[3:0] MEMLAT and CFR3N[7:6] to the appropriate settings.

regards,
IFX) Yuka Ami

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Thanks for your quick response. 

I tried the configuration you suggested & unfortunately, it got worse. Somehow, the chip cannot be identified (RDIDN_0_0/RDQID_0_0) in any mode, tried 1-1-1, 1-1-4, 1-4-4, 4-4-4, everything always is read back as 0xff with and without latency. Only in 4-4-4 mode without latency, RDIDN_0_0  for a 3 byte read returns [0x0, 0xff, 0xff], which is strange. 

Reading all the configuration & STR registers in 4-4-4 mode without latency returns 0x0. However, if I try a WRENB_0_0 to enable the writes, it fails and STR1 always has 0x0 value. 

I am not sure what is going on with the chip at the moment and how to recover it. Do you have any other suggestions?

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Yuvraj
Moderator
Moderator
Moderator
First question asked 250 replies posted 25 likes received

Hi,

can you please read the device ID with SPI and QSPI?


If it is possible Please provide a waveform.

until and unless we don't see the waveform it will be difficult to understand what is going wrong.

Regards,

Yuvraj 

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Hi,
I tried reading it, however it reads back 0xff for both SPI and QSPI. 

Unfortunately, it is not possible to provide waveforms since the chip is unaccesssible. 

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KatsumasaH_16
Employee
Employee
10 solutions authored First comment on KBA 50 sign-ins

Hi

Read the settings in the status and configuration registers and please check the current settings.

Best regards,
Honjo

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Hi,
I did try reading the status and configuration registers in both SPI and QSPI mode, all are read back as 0xff. Only in 4-4-4 mode with 0 latency cycles, the status and configuration registers read back as 0x0. 

Thank you

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Yuvraj
Moderator
Moderator
Moderator
First question asked 250 replies posted 25 likes received

Hi,

What you stating here is correct. This is what is expected,  You will not be able to read or operate in SPI or QSPI mode.


Once the device is set in 4-4-4 mode if you want to set it in SPI or QSPI mode you need to 
change CFR2N[6] / CFR2V[6].

To change these bits you have to use write commands as per 4-4-4 (QPI) mode.

Make sure you write the configuration register as per QPI commands.

Regards,

Yuvraj 

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

If I am already in QPI mode, why does RDIDN_0_0/RDQID_0_0 in 4-4-4 mode does not respond with the correct value then? When I try to read 3 bytes by sending RDIDN_0_0/RDQID_0_0, all I read is

0x0

0xff

0xff

which is incorrect. Why is this the case?

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Yuvraj
Moderator
Moderator
Moderator
First question asked 250 replies posted 25 likes received

Hi,

Can you please clear all the bits from the configuration and status register? (Make all the bits of these registers default values) by using QPI commands.

Then exit the QPI mode.

Sometimes what happens is that if there is a abrupt power down during register write operation, bits in the register might get corrupted which results in unexpected behaviour.

Regards,

Yuvraj 

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

The issue is that I am unable to enable writes by sending WRENB_0_0 QPI command. The STR1 register stil reads back as 0x0, which means the WRPGEN could not be set by sending this command. Therefore, cannot even clear the configuration and status registers.

Is there some other solution to exit QPI mode? Can you help me with a QPI mode disable or exit sequence in this case? 

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YukaA_81
Employee
Employee
5 solutions authored 10 replies posted First like given

Hi,

STR1 is a volatile register, and the latency cycle should refer to the table below.

YukaA_81_0-1698040930012.png

 

Also, based on the results below, the latency setting related to STR1 read is "11" and requires 2 cycles From the table above.

     CFG1: 0x2 /  QSPI enable
    CFG2: 0xd8 / 4byte mode enable, QPI mode enable, Non volatile latency default=1000
    CFG3: 0xd2 / 512byte WB, volatile latency=11,
    CFG4: 0x0   / 1bit ECC error detection & correction

Have you already tried STR1 with 2cyle latency?

regards,
Yuka Ami

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Hi,

Yes, I have tried that with 2cycle latency, I read STR1=0xff. Infact, STR2, CFG1, CFG2, CFG3, CFG4 also are read back as 0xff with 2cycle latency.

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Yuvraj
Moderator
Moderator
Moderator
First question asked 250 replies posted 25 likes received

Hi,

Registers might be corrupted due to abrupt power down.

Can you read in QPI mode with different latency cycles example 0, 1,2 etc?

Regards,

Yuvraj  

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Hi,
Thank you for your response. 


With 0 latency cycle, all values are 0x0.
With 1 latency cycle, all values are 0x8f.

With 2 latency cycles and onwards, all values are 0xff. 

Thanks

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Yuvraj
Moderator
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Moderator
First question asked 250 replies posted 25 likes received

Hi,

What are all values? are you talking about various register values?

Regards,

Yuvraj 

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Yes, by values I mean the values read from STR1, CFG1-4 registers.

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Yuvraj
Moderator
Moderator
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First question asked 250 replies posted 25 likes received

Hi,

Can you please read the device id using various latency cycles?

See on which latency cycles you are getting correct device ID.

Regards,

Yuvraj 

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Since the maximum can be 3 latency cycles for a RDIDN read, below are the values I read in QPI mode:

Latency cycles

Value Read

0

Manufacturer ID: 0x0
Device ID MSB: 0xff
Device ID LSB: 0xff

1

Manufacturer ID: 0x8f
Device ID MSB: 0xff
Device ID LSB: 0xff

2

Manufacturer ID: 0xff
Device ID MSB: 0xff
Device ID LSB: 0xff

3

Manufacturer ID: 0xff
Device ID MSB: 0xff
Device ID LSB: 0xff

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

Hi,
One question, since our QPI commands don't work, is there another way to reset the non-volatile values in the configuration registers without the QPI commands?

Thanks

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Yuvraj
Moderator
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First question asked 250 replies posted 25 likes received

Hi,

It looks like you have corrupted the registers.

Now the unique way to recover from this state is to use the SafeBoot sequence which is detailed in the datasheet.

Please follow the procedure in the datasheet.



Regards,
Yuvraj 

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

I am trying out the safeboot sequence, however in 1S-1S-1S mode, I am unable to clear the STR1 register. The value is still read back as 0xff. How can I make it work?

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svr
Level 2
Level 2
10 replies posted 5 sign-ins 5 replies posted

I am confused now, what do you mean by safe booting the flash first? Isn't this the safeboot sequence to follow if there is a configuration corruption? It expects you to clear the STR1 register in 1S-1S-1S mode.

svr_0-1698312533167.png

 

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Yuvraj
Moderator
Moderator
Moderator
First question asked 250 replies posted 25 likes received

Hi,


It looks like you have corrupted the FLASH which can't be recovered now.

We recommend replacing the faulty FLASH with a new FLASH.

Just make sure you don't do register write while booting every time.

Register writing is very vulnerable if you do it again and again while booting up FLASH might get currupted. 

Regards,

Yuvraj 

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