Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

Nor Flash Forum Discussions

DaNe_4783256
Level 1
First solution authored
Level 1

Hello,

I am using S25FL512SAGBAEA10 SPI flash and I have a question based on the timing with the write enable command (06h) and the page program (02h). Essentially I am wondering how long do I have to wait before sending a page program command after sending the write enable command. I just want to write a file to the SPI flash.

The datasheet says "CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not be executed". This statement I feel is true but doesnt tell you everything you need to know. I have tried to follow this with a page program command immediately after sending a write enable command and it has not worked even when I have comfirmed that the CS# goes back high in between with a 20 ns delay in between. Is there some delay I need to have in between the commands so that the write enable actually executes? Is it based off SCK? I'm trying to find this in your datasheet but I'm failing to find it. I'm using Document Number 001-98284 Rev *Q.

Note: I can set the write enable bit but theres some timing relationship between commands that must be getting violated.

In the meantime I am going to try a 100 ns second delay to see if that fixes things and try to re-read the datasheet and try to get the simulation model for the SPI flash working.

Thanks, Dan

0 Likes
1 Solution
DaNe_4783256
Level 1
First solution authored
Level 1

could it be because im not preloading the memory again and the memory is defaulted to Xs?

View solution in original post

0 Likes
4 Replies
DaNe_4783256
Level 1
First solution authored
Level 1

It seems like the write enable commands work in the simulation model but I'm having some problems with the read command (03h). I'm using the VHDL simulation model and it seems to be outputting unknowns (Xs) when I'm expecting read back data. Is there any reason for this? I'm trying to figure out why what I'm doing wrong. The serial clock is 12.5 MHz so it should work or at least thats what i was expecting. See simulation below.

spi_flash_read.PNG

0 Likes
DaNe_4783256
Level 1
First solution authored
Level 1

could it be because im not preloading the memory again and the memory is defaulted to Xs?

0 Likes
WaHo_4359701
Level 1
Level 1

From my memories, you don't have to wait for write enable command and you can start to write or erase immediately

Suggestions:

1.if you use simulation model, see if the instructions(06h or others) you send in is correct. Then check for the status register 1 (SR1) bit (WEL) to see if you send write enable(WREN) successfully

2.if you send WREN successfully, then you can start writing.

Notice Page Program operation needs time to finish, you can read status register 1(SR1) bit (WIP) to check if it's finish. 

You can find the time specifications from Embedded Algorithm Performance Tables, which gives out the typical and maximum time. In reality,  the time spent might be a little bit different, but you can read WIP to check for the real time.

3.if you find WIP hold high while you write in(Page Program) and after some time(us) it goes low, it means you already write in what you want.

0 Likes
AlbertB_56
Moderator
Moderator 500 replies posted 50 likes received 250 replies posted
Moderator

Hello,

For some reason I am receiving this thread, just now.

Has this issue been addressed/resolved?

Please advise...

 

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

 

0 Likes