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When using S25FL512S (NOR flash) with Xilinx Virtex 7 is it recommended to use same VIO supply as SPI bank supply on Virtex 7?
According to Connecting Cypress SPI Serial Flash to Configure Xilinx FPGAs document:
"Because tPU is an order of magnitude less than TPOR, the SPI flash becomes ready before the FPGA issues the read command if the same power rail supplies both FPGA and SPI flash. If not, a countermeasure may be needed".
What will happen if the voltage to flash becomes active after the SPI bank voltage on FPGA?
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Serial NOR
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Hi Mats,
As you see in the Xilinx document, the flash should be ready when the FPGA is powered up. It is recommended to use the same Vio as the SPI bank. If the flash is not Power On Reset yet when FPGA issues the first read command to get configuration data from the flash, wrong data may be returned from flash and the FPGA may not be configured properly.
In short, you have to make sure the flash is initialized properly before the first read command issued from the FPGA.
Hope this answers your question.
Thanks,
Zhi
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Hello Mats,
Thank you for contacting Cypress Community Forum. We have received your inquiry and currently reviewing the issue. We will get back to you as soon as we find the resolution.
Have a wonderful day
Regards,
Bushra
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Hi Mats,
As you see in the Xilinx document, the flash should be ready when the FPGA is powered up. It is recommended to use the same Vio as the SPI bank. If the flash is not Power On Reset yet when FPGA issues the first read command to get configuration data from the flash, wrong data may be returned from flash and the FPGA may not be configured properly.
In short, you have to make sure the flash is initialized properly before the first read command issued from the FPGA.
Hope this answers your question.
Thanks,
Zhi
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Thanks for the quick answer.
How about the VCC supply input on the NOR flash? As i understand from the datasheet the VCC must reach the correct values before being selected =>
Power seq:
1. VCC (3.3V)
2. VIO and FPGA bank supply (1.8V)
Is this correct understood?
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Hi Mats,
Yes, that is true. Usually if you have a pull-up resistor on CS# pin, it will track Vio during power-up. You should also make sure Vio is always less than Vcc during POR. Those are typical power up requirements.
Thanks,
Zhi
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So either use 3.3V to VCC and 1.8V to VIO and FPGA bank and make sure that VCC reach the correct values bere being selected OR use same voltage on all (3.3V). Correct understood?
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Hi Mats,
I don't quite understand your questions, but I would try to answer generally. If you still have questions, please put them in a simpler form.
1. Because you are using FL-S, the Vcc needs to be 3.3V
2. Vio would depend on the IO voltage of the FPGA. I think it is 1.8V on Virtex 7.
3. You will need a weak pull-up on the CS# signal.
4. Your circuit design should make sure Vio would not exceed Vcc at any time.
Thanks,
Zhi
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1. According to datasheet i can use same voltage on VIO and VCC on FL-S to get maximum read rates. So VIO can be equal to VCC=3.3V. Correct?
Thanks
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Yes. That is correct. Flash Vio can be the same as Vcc.
Thanks,
Zhi