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Nor Flash

Anonymous
Not applicable

We recently switched a board from the S25FL512S to the S25FL256S / 256kbit sector option, and have noticed that after a Bulk Erase or 4SE command, the flash will respond to a RDSR1 command with all bits set the first time, and then subsequent reads of RDSR1 will correctly show the WIP bit and write success, error bits will be 0 etc. We never saw this on the S25FL512S, code is basically the same.

Inserting a few (2-3) dummy reads of RDSR1 seems to be working as a work around, we're able to poll WIP after the first dummy read.

Is it normal to sometimes read the status register as all bits set / will the flash not drive the status register bits sometimes (we do have 1k pullups on MISO)? Is there a minimum wait time between bulk erase and polling RDSR1? SPI frequency is 2.5MHz, both mode 0 and mode 3 act the same. Flash is factory default settings afaik.

Thanks,

Jacob

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1 Solution
TakahiroK_16
Employee

Hi Jacob,

Please verify if an AC parameter tCS, CS# High Time (Program/Erase) = 50ns, is satisfied in your board.

This would be an answer to your question, "Is there a minimum wait time between bulk erase and polling RDSR1?".

The S25FL512S and S25FL256S has same tCS parameter, however, if the timing is marginal, you may see the device to device variation (some devices pass and some devices fails).

Best Regards,

Takahiro

View solution in original post

2 Replies
TakahiroK_16
Employee

Hi Jacob,

Please verify if an AC parameter tCS, CS# High Time (Program/Erase) = 50ns, is satisfied in your board.

This would be an answer to your question, "Is there a minimum wait time between bulk erase and polling RDSR1?".

The S25FL512S and S25FL256S has same tCS parameter, however, if the timing is marginal, you may see the device to device variation (some devices pass and some devices fails).

Best Regards,

Takahiro

View solution in original post

Anonymous
Not applicable

Ok, thanks. It turns out there was a previously un-noticed bug in our SPI driver that was not releasing nCS correctly, so it was a nCS timing issue. It looks like it is working now.

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