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Yan
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Hello everyone,

I am currently using an s25fl256s flash memory, but when I try accessing it (using an SPI master on an Artix7 FPGA) the first read access has a delay of 19 clock cycle (more or less) and afterward the data is received correctly, does anyone know what causes the delay on the first read access ? According to the datasheet (Figure 67 Read command sequence (3-byte address, 03h [ExtAdd = 0])) there should be no delays : https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Fl...

 

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Yuvraj
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Hi,

Thank you for contacting Infineon Technologies.

Can you please provide the waveform of the operation? 

Regards,

Yuvraj 

Yan
Level 1
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Hi Yuvraj,

Thank you for yoour quick reply.

I did but I am only using the basic read command x"03", and the delay happens only on the first access to the memory after that, every read access happens with no delay, please refer to the screenshot below

Yan_0-1670232042554.png

In this screenshot you can see two read access to the address x"000001", the first one has a delay of 19 clock cycles, and the second one happens correctly (I am expecting to read x"53")

Best regards

Yan

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Yuvraj
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Hi,

Which operation performing before the read operation,


Can you please check the status register status? before passing the read command?

 

Regards,

Yuvraj 

Yan
Level 1
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Hi,

Before the read command I just have a 5 seconds delay (with no command) before I start reading the flash. The read statut command seems  have a 2 clock cycles delay please refer to the screenshot below

Yan_0-1670247664618.png

Best regards

Yan

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Yuvraj
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Hi Yan,

Could you please let us know what is the clock frequency?

Please try at lower clock frequency.

 

Regards,

Yuvraj 

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Yan
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Hi Yuvraj,

In the screenshot the frequency is 25 MHz but I have the same issue with lower frequencies.

Best regards,

Yan

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Yuvraj
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Hi Yan,

How many devices have you tested? Is it possible to replace the Flash and check this behavior?

 

Regards,

Yuvraj

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