S25FL256S - DLP

[avhoc_4004001]

Problem.

The address of the documentation is http://www.cypress.com/file/448601/download page 96, an additional parameter for reading DLP, in DDR Quad I / O mode Read 4-byte Address. I do not understand the purpose of the DLP. Who gives the DLP, the purpose and application.

I need to run a fast read in the DDR Quad I / O Read 4-byte Address mode together with the stm32f7 chip.

The stm32f7 chip has hardware support for DDR Quad, with the mode of direct mapping of the address space (no separate reading functions are required). And also the mode of fast reading. This is when the instruction before the address is not sent, the chip is snapped to the place of this in read mode, and each call to the chip always occurs in read mode. Exiting this mode is the magic of reading a series of addresses in strict sequence.

I could not detect a similar mode for the S25FL256S chip. The instruction seriously slows down the speed of reading.

[SudheeshK · Accepted solution]

Hi,

I hope your query is about eliminating the need to send "READ" instruction while reading data continuously. Our device S25FL256S has this feature and it is called "Execute in place (XIP)". Entering and exiting this mode is controlled by the mode bits. Please see the paragraph from datasheet below.

"The Mode bits control the length of the next Read DDR Quad I/O operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous Read DDR Quad I/O Mode and the next address can be entered (after CS# is raised HIGH and then asserted LOW) without requiring the EDh or EEh instruction, as shown in Figure 99 on page 96 and Figure 101 on page 97 thus, eliminating eight cycles from the command sequence. The following sequences will release the device from Continuous Read DDR Quad I/O mode; after which, the device can accept standard SPI commands:

1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the next time CS# is raised HIGH and then asserted LOW the device will be released from Read DDR Quad I/O mode.

2. During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0, IO1, IO2, and IO3) are not set for a valid instruction sequence, then the device will be released from Read DDR Quad I/O mode."

Please refer section "9.4.9 DDR Quad I/O Read (EDh, EEh)" on page 95 of datasheet (https://www.cypress.com/file/448601/download ) for more details. I hope this information answers your query.

Thanks and Regards,

Sudheesh

[avhoc_4004001]

Thank you for your reply.