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【use】
STM32H723S25FL256LAGMFI003
document
Number: 002-00124 Revised Edition * H
I am currently writing a write / read check program using S25FL256LAGMFI003.
Writing / reading from 0x00000000 to 0x01FFFFFE seems to be successful.
, Clear / write seems to fail only at 0x01FFFFFF.
We considered the possibility of write protection.
So I checked the values in the status register and the settings register, but the initial values were read.
STATUS1 = 0x00
Statsu2 = 0x00
CONFIG1 = 0x00
CONFIG2 = 0x00
CONFIG3 = 0x78
Next, we considered the possibility of being protected by the pointer area protection register.
However, the register read command (0x65) must read the pointer area protection register successfully.
I stumbled further here. The address read command is only partially successful.
First, I read status register 1 using any register read command and it succeeded.
Then I read configuration register 1, but couldn't read the value.
1. Isn't the final address (0x01FFFFFF) writable for protection? Or is it an area that cannot be written in the first place?
2. Do you know why the register read command (0x65) fails?
Solved! Go to Solution.
- Labels:
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Memory Nor Flash
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Hello,
The source code and CE (Chip Erase) sequence look good. However, Configuration Register 2 value does not seem correct.
- I'm using a 4-byte address access mode.
Just in case, I checked the value of config register2.
Confirmed that CR2V [0] = 1.
We do see in the log, CR2=0x61. But CR2[0] is Reserved bit which default value should be 0. CR2V[1] sets the address mode, and it is 0 in the log, which indicates it is 3-byte address mode. How did you enable 4-byte address mode? i.e., set CR2V[1] = 1, or sent Enter 4 Byte Address Mode command (4BEN B7h)?
It was confirmed that the following settings were made in the config register 3.
CR3V [3] = 1
CR3V [2] = 0
CR3V [1] = 0
CR3V [0] = 0
Does this fit the idea of sending 8 bits of empty data?
Dummy cycle refers to clock cycles. CR3V[3:0]= 1000b, means 8 dummy (clock) cycles. In single IO mode, it is 8 bits dummy data. It could be 16 bits or 32 bits data in dual or quad mode.
Dummy cycle is only required for flash memory array read commands and RDAR command, not required for write commands. The host does not need to send any dummy data to flash. It indicates the clock cycles the host needs to wait to sample the output data after sending read command sequence (command + address).
Thank you
Regards,
Bushra
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Hello,
Thank you for contacting Infineon Technologies. Can you please send us the screenshot of the error if possible? Also is it possible to share the code?
Regards,
Bushra
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thank you for your reply.
This screenshot was taken when all addresses were cleared / written / read
This is the confirmation screen of the debugger.
The page program command was executed once for all addresses.
It is then read page by page and checked to see if the written values match.
Fails with a check error when reading the last address
Please check the source code.
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Hello,
The source code and CE (Chip Erase) sequence look good. However, Configuration Register 2 value does not seem correct.
- I'm using a 4-byte address access mode.
Just in case, I checked the value of config register2.
Confirmed that CR2V [0] = 1.
We do see in the log, CR2=0x61. But CR2[0] is Reserved bit which default value should be 0. CR2V[1] sets the address mode, and it is 0 in the log, which indicates it is 3-byte address mode. How did you enable 4-byte address mode? i.e., set CR2V[1] = 1, or sent Enter 4 Byte Address Mode command (4BEN B7h)?
It was confirmed that the following settings were made in the config register 3.
CR3V [3] = 1
CR3V [2] = 0
CR3V [1] = 0
CR3V [0] = 0
Does this fit the idea of sending 8 bits of empty data?
Dummy cycle refers to clock cycles. CR3V[3:0]= 1000b, means 8 dummy (clock) cycles. In single IO mode, it is 8 bits dummy data. It could be 16 bits or 32 bits data in dual or quad mode.
Dummy cycle is only required for flash memory array read commands and RDAR command, not required for write commands. The host does not need to send any dummy data to flash. It indicates the clock cycles the host needs to wait to sample the output data after sending read command sequence (command + address).
Thank you
Regards,
Bushra
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Hello,
What is the result when using the RDCR1 (command : 35h) to read Config. Regist.-1?
Are you able to successfully read all "F's" when initiating a Chip Erase?
Best regards,
Albert
Cypress Semiconductor Corp.
An Infineon Technologies Company
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thank you for your reply.
The value read by RDCR1 (command: 35h) is saved in reg_cnf1 of the image.
Screenshots were taken before and after executing the chip erase command.
For the value of config register 1, 0x00 was read both before and after the clear command.
Also, read the "F" at all addresses to see if it succeeded before running the chip erase command. As a result, it was successful.
After running the chip erase command, I confirmed the same thing. As a result, I was able to read all the "F" s and succeed.
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Hello,
Please see below:
“Clear / write seems to fail only at 0x01FFFFFF”
- Do you mean only fail at this specific byte address? If yes, then it is not write protection. The minimum memory array write protection granularity is 4KB sector size.
- How did you do Clear? Can you please share us the command sequence for “Clear”? What’s the data at 0x01FFFFFF before and after “Clear”?
- What address (3-byte address or 4-byte address) commands did you use? 3-byte address can only access the lower 128Mb (16MB) memory space. To access the upper 128Mb (16MB) memory space, three options as below:
- Use 4-Byte address commands + 4-byte address (refer to table 39 in the datasheet)
- Send Enter 4 Byte Address Mode command (B7h), then use 3-Byte address commands + 4-byte address
- Set CR2N[1]=1 to enable 4-byte address mode, then use 3-Byte address commands + 4-byte address
- Isn't the final address (0x01FFFFFF) writable for protection? Or is it an area that cannot be written in the first place?
- The final address is the same as all other memory array space. It is writable.
- Do you know why the register read command (0x65) fails?
- The command should be followed by a 3 or 4 Byte address (depending on the address length configuration CR2V[0]), followed by a number of latency (dummy) cycles set by CR3V[3:0]. Please check if all these are satisfied.
Thank you
Regards,
Bushra
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- Do you mean only fail at this specific byte address? If yes, then it is not write protection. The minimum memory array write protection granularity is 4KB sector size.
- The final address is the same as all other memory array space. It is writable.
thank you. This solved one of my concerns.
- How did you do Clear? Can you please share us the command sequence for “Clear”? What’s the data at 0x01FFFFFF before and after “Clear”?
I have performed the following steps:
1. Set CS low
2. Executing the WREN command
3. Set CS high
4. Set CS low
5. Execution of CE command
6. Set CS high
- What address (3-byte address or 4-byte address) commands did you use? 3-byte address can only access the lower 128Mb (16MB) memory space. To access the upper 128Mb (16MB) memory space, three options as below:
I'm using a 4-byte address access mode.
Just in case, I checked the value of config register2.
Confirmed that CR2V [0] = 1. - The command should be followed by a 3 or 4 Byte address (depending on the address length configuration CR2V[0]), followed by a number of latency (dummy) cycles set by CR3V[3:0]. Please check if all these are satisfied.
I seem to lack an understanding of the dummy cycle.
It was confirmed that the following settings were made in the config register 3.
CR3V [3] = 1
CR3V [2] = 0
CR3V [1] = 0
CR3V [0] = 0
Does this fit the idea of sending 8 bits of empty data?