S25FL256L getting 0xFF value for status 1 & status 2 register read command in page write.

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SnehalB
Level 1
Level 1
First reply posted First question asked Welcome!

Hi,

we are using S25FL256L QSPI flash with intel Cyclone  V E fpga, we have written a script for FLash programming via JTAG mode from Quartus programmer. Our Read ID, auto detect as QSPI256mb flash , blank check process is successfully completing but failing in Program stage.

Programming fails at around 33% programming done, below is the error we get 

"Error (20064): Error status: Read status 2 register returned 0xFF is mismatch with the expected data (0x00) Error (19117): Programming failed on flash 1 at address 0x00BB0100 Error (209012): Operation failed"

when we read status 1 register(0x05) and status 2 register (0x07) we are getting value returned as 0XFF at address 0x00BB0100 . we are using 0x12 command for 4byte addressing mode page write. for address previous to 0x00BB0100 is ok we are not getting error ,as we added read status 1 register(0x05) and status 2 register (0x07) for it.

 

can you please suggest us , what can be probable reason for that error.

thanks,

Snehal B.

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1 Solution
Yuvraj
Moderator
Moderator
Moderator
250 replies posted 25 likes received 100 solutions authored

Hi Snehal,

Please provide Waveform (Logic traces) of the operations you are performing.

We recommend doing polling after erase and programming operation.
And also, it is not recommended to give delay could you please let us know why you are providing delay after giving certain commands?

 

Regards,

Yuvraj

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4 Replies
Yuvraj
Moderator
Moderator
Moderator
250 replies posted 25 likes received 100 solutions authored

Hi Snehal,

Thank you for contacting Infineon Technologies.

Can you please provide the waveform of the operation you are performing on FLASH.

 

Regards,

Yuvraj 

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SnehalB
Level 1
Level 1
First reply posted First question asked Welcome!

please check posted reply below for same problem

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SnehalB
Level 1
Level 1
First reply posted First question asked Welcome!

Hi , 

we will provide you the requested waveforms.

But additionally, We try to implement flash programming through intel quartus jtag programmer based on application note by infineon.
Application Note AN229767 Enabling Infineon QSPI Flash to Configure Intel Cyclone 10 GX FPGA @ https://www.infineon.com/dgdl/Infineon-AN229767_Enabling_Infineon_QSPI_Flash_to_Configure_Intel_Cycl...

 

Accordingly, we implemented for S25FL256L and are successfully getting  Read ID, Auto detect as QSPI256mb flash in jtag chain, blank check verification process is successfully completing but failing in Program write stage. And Program write fails always at fix address 0x00BB0100. (after 36% program write progress in quartus programmer)

below is the error  

"Error (20064): Error status: Read flag register returned 0xFF is mismatch with the expected data (0x00) Error (19117): Programming failed on flash 1 at address 0x00BB0100 Error (209012): Operation failed"

Below are snapshot of instruction and opcode we used in settings

Initialization step

SnehalB_0-1672659683163.png

SnehalB_1-1672659692562.png

ERASE

SnehalB_2-1672659711966.png

Verification/read/blank check

SnehalB_3-1672659752412.png

 



Programming write

SnehalB_4-1672659783434.png

SnehalB_5-1672659794356.png

Could you please check and revert if we missing anything for doing any wrong process. Also programming is continuous and automated, so if any timing error then should be at previous addresses only, but its failing always at fix address.

kindly support!


Thanks & Regards,
Snehal B.

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Yuvraj
Moderator
Moderator
Moderator
250 replies posted 25 likes received 100 solutions authored

Hi Snehal,

Please provide Waveform (Logic traces) of the operations you are performing.

We recommend doing polling after erase and programming operation.
And also, it is not recommended to give delay could you please let us know why you are providing delay after giving certain commands?

 

Regards,

Yuvraj

0 Likes